View SI4010-C2_4661384.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 1.0 2/11 copyright ? 2011 by silicon laboratories si4010 SI4010-C2 c rystal - less s o c rf t ransmitter features applications description the si4010 is a fully integrated crystal -less cmos soc rf transmitter with an embedded cip-51 8051 mcu. the device can operate over the ?40 to 85 c temperature range withou t requiring an external crystal reference source reducing board area and bom cost. the device includes an 8 kb non volatile memory block for programming the user's application along with a 12 kb rom of embedded support code for use in the user's appl ication. the si4010 includes silicon laboratories' 2-wire c2 debug and programming interface, which allows customers to download their code during the development stage into the on-board ram for testing and debug prior to programming the nvm. the si4010 is designed for low power battery applications with standby currents of less than 10 na to optimize battery life and f eatures automatic wake on button press support to efficiently move from the standby to active mode state with minimal customer code support. built in aes-128 hardware encryption along with a 128-bit eeprom can be used to create robust data encryption of the transmitted packets. a unique 4-byte serial number is programmed into each device ensuring non-overlapping device identifiers. the rf transmitter features a high efficiency pa capable of delivering output power up to +10 dbm and includes an automatic antenna tuning algorithm. this algorithm adjusts the antenna tuning at the start of each packet transmission for optimal output power minimizing the im pact of antenna impedance changes due to the remote being held in a user hand. the devices supports fsk and ook modulations and includes aut omatic output power shapi ng to reduce spectral spreading and ease regulatory complianc e. the output frequency can be adjusted via software over the entire 27 to 960 mhz range. the output data rate is software adjustable up to a maximum rate of 100 kbps. ? crystal-less operation ?? optional crystal oscillator input ? high-speed 8051 c core ?? pipeline instruction architecture ?? 70% of instructions in 1 or 2 clocks ?? up to 24 mips with 24 mhz clock ?? 4 kb ram/8kb nvm ?? 128 bit eeprom ?? 256 byte of internal data ram ?? 12 kb rom embedded functions ?? 8 byte low leakage ram ? extensive digital peripherals ?? 128 bit aes accelerator ?? 5/9 gpio with wakeup functionality ?? led driver ?? data serializer ?? high-speed frequency counter ?? on-chip debugging: c2 ?? unique 4 byte serial number ?? ultra low-power sleep timer ? single coin-cell battery operation ?? supply voltage: 1.8 to 3.6 v ?? standby current < 10 na ? high-performance rf transmitter ?? frequency range: 27?960 mhz ?? +10 dbm output power, adjustable ?? automatic antenna tuning ?? symbol rate up to 100 kbps ?? fsk/ook modulation ?? manchester, nrz, 4/5 encoder ? analog peripherals ?? ldo regulator with por circuit ?? battery voltage monitor ? temperature range ?40 to +85 c ? automotive quality option, ? aec-q100 (pending final qualification testing) ? 10-pin msop/14-pin soic ? garage and gate door openers ? remote keyless entry ? home automation and security ? wireless remote controls patents pending ordering information: see page 15 . pin assignments gpio0/xtal si4010-gt 2 3 6 7 8 4 5 9gpio2 gpio3 gpio4 led vdd txp gnd txm 1 10 gpio1 si4010-gs 3 4 9 10 11 5 6 12 gpio2 gpio3 c2dat/gpio4 c2clk/led vdd vpp/gpio0/xtal txp gnd txm 2 13 gpio1 gpio9 1 14 gpio8 8 7gpio6 gpio7 14-pin soic 10-pin msop
SI4010-C2 2 rev. 1.0 functional block diagram si4010 nvm 8 kbyte eeprom 128-bit vdd gnd pa ram/ rom push buttons cr2032 coin cell 1.8 ? 3.6 v divider i/o interface gpio 4/8 integrated 8051 mcu ldo regulator txm txp loop antenna fsk ook led vdd
SI4010-C2 3 rev. 1.0 t able of c ontents 1. system overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2. test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3. typical application schemati c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.1. si4010 used in a 5-button rke s ystem with led indica tor . . . . . . . . . . . . . . . . . . . 14 3.2. si4010 with an external crystal in a 4-button rke system with led indicator . . . . 14 4. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 5. top markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1. soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2. msop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6. pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1. msop, application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.2. msop, programming/debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3. soic package, ap plication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.4. soic package, pr ogramming/debug mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7. package specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.1. 10-pin msop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.2. 14-pin soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8. pcb land pattern 10-pin msop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9. pcb land pattern 14-pin soic package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10. electrical character istics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11. system description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 11.1. overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 11.2. setting basic si4010 transmit parame ters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11.3. applications program ming interface (api) commands . . . . . . . . . . . . . . . . . . . . . . 35 12. power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 12.1. register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 13. output data serializer (ods ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 13.1. description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 13.2. timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 13.3. register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 14. lc oscillator (lcosc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 14.1. register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 15. low power oscillator and system clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 15.1. register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 16. crystal oscillator (xo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 16.1. register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 17. frequency counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 17.1. register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 18. sleep timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 19. bandgap and ldo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 20. low leakage hvram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 21. temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 22. cip-51 microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
SI4010-C2 4 rev. 1.0 22.1. instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 22.1.1. instruction and cpu timing........... ................. .............. .............. .............. .......... 56 22.2. cip-51 register descripti ons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 23. memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 23.1. program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 23.2. internal data memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 23.3. external data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 23.4. general purpose register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 23.5. bit addressable locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 23.6. stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 23.7. special function regist ers (sfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 23.8. registers mapped to xdata a ddress space (xreg) . . . . . . . . . . . . . . . . . . . . . . 67 23.9. nvm (otp) memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 23.10. mtp (eeprom) memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 24. system boot and nv m programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 24.1. startup overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 24.2. reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 24.3. chip program levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 24.4. nvm organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 24.5. device boot proces s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 24.6. error handling during boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 24.7. code/xdata ram address map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 24.8. boot status variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 24.9. boot routine destinat ion address space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 24.10. nvm programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 24.11. retest and retest configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 24.12. boot and retest protection nvm control byte . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 24.13. chip protection control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 25. on-chip registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 25.1. special function register s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 25.2. xreg registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 26. interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 26.1. mcu interrupt sources a nd vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 26.2. interrupt priorities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 26.3. interrupt latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 26.4. interrupt register descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 26.5. external interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 27. power management modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 27.1. idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 01 27.2. stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1 28. aes hardware accelerat or. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 28.1. aes sfr registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 29. reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 29.1. device boot outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 29.2. external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 29.3. software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
SI4010-C2 rev. 1.0 5 30. port input/output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 30.1. gpio pin special roles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 30.2. pullup roff option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 30.3. matrix mode option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 30.4. pullup roff and matrix mode option control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 30.5. special gpio modes control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 30.6. led driver on gpio[5]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 31. clock output generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 31.1. register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 32. control and system setting registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 33. real time clock timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 33.1. rtc interrupt flag time uniformity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 33.2. register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 34. timers 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 34.1. interrupt flag generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 34.2. 16-bit timer with auto reload (wide mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 34.3. 16-bit capture mode (wide mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 34.4. 8-bit timer/timer mode (split m ode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 34.5. 8-bit capture/capture mode (spl it mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 34.6. 8-bit timer/capture mode (split mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 35. c2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 35.1. c2 pin sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 36. ide development environment an d debugging chain . . . . . . . . . . . . . . . . . . . . . . . . 151 36.1. functionality limitations while using ide deve lopment environment . . . . . . . . . 151 36.2. chip shutdown limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 36.3. led driver usage while usi ng ide debugging chain . . . . . . . . . . . . . . . . . . . . . . 152 37. additional reference resour ces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156
SI4010-C2 6 rev. 1.0 l ist of f igures figure 1.1. si4010 block diagram ....... ................ ................. .............. .............. .............. .......... 12 figure 2.1. test block diagr am with 10-pin msop ... ................. ................ ................. ............ 13 figure 3.1. si4010 used in a 5-butt on rke system with led indicator ................... ............... 14 figure 3.2. si4010 with an external crystal in a 4-butt on rke system with le d indicator ..... 14 figure 1. si4010 top marking ........... ................ ................ .............. ............... .............. ............ 16 figure 2. si4010 top marking ........... ................ ................ .............. ............... .............. ............ 17 figure 7.1. 10-pin msop pa ckage ................. ................ ................ ................. .............. ..........22 figure 7.2. 14-pin soic pack age .............. ................ ................. ................ ................. ............ 23 figure 8.1. 10-pin msop recomm ended pcb land pattern ..... ................ ................. ............ 24 figure 9.1. 14-pin soic recommended pcb land pattern .............. .............. .............. .......... 26 figure 11.1. functional block diagram ............... ................. .............. .............. .............. .......... 33 figure 12.1. simplified pa block diagr am ................. ................. ................ ................. ............ 36 figure 13.1. ook timing exam ple ................. ................ ................ ................. .............. ..........40 figure 13.2. fsk timing example ...... ................ ................. .............. .............. .............. .......... 40 figure 17.1. frequency counter block di agram ............. ................ ................. .............. .......... 50 figure 22.1. cip-51 block diagram ..... ................ ................. .............. .............. .............. ..........55 figure 23.1. address space map after the boot ........ ................. ................ ................. ............ 65 figure 24.1. nvm address map .......... ................ ................. .............. .............. .............. .......... 72 figure 24.2. code/xda ta ram address map ......... ................. ................ ................. ............ 75 figure 24.3. boot routin e destination cpu a ddress space for copy from nvm .......... .......... 79 figure 30.1. device package and port assignments ............. .............. .............. ............ ........ 108 figure 30.2. gpio[3:1] functional diagr am ............... ................. ................ ................. .......... 110 figure 30.3. other gpio functional diagram ................... .............. ............... .............. .......... 110 figure 30.4. push bu tton organization in matr ix mode ............... ................ ................. .......... 113 figure 30.5. gpio[5] led dr iver block diagram .......... ................ ................. .............. ..........117 figure 31.1. output clock generator block diagram ........ .............. ............... .............. .......... 123 figure 33.1. rtc timer bloc k diagram .............. .............. .............. ............... .............. ..........128 figure 34.1. timer interrupt generation ............ ................ .............. ............... .............. ..........132 figure 34.2. timer 16-bit mode block diagram (wide mode) .............. .............. ............ ........ 133 figure 34.3. capture 16-bit mode bl ock diagram (wide mode) ............... ................ ............. 134 figure 34.4. two 8-bit timers in timer/timer configuration (split mode) .............. ............... 135 figure 34.5. two 8-bit timers in capture/capture confi guration (split mode) .............. ........ 136 figure 34.6. two 8-bit timers in timer/capture configurat ion (split mode) .... ............. ........ 137 figure 34.7. two 8-bit timers in capture/timer configurat ion (split mode) .... ............. ........ 138 figure 35.1. 10-pin c2 us b debugging adapter connection to devi ce ............... ................. 148 figure 35.2. 14-pin c2 toolstick connection to devi ce ................. ............... .............. .......... 150
SI4010-C2 rev. 1.0 7 l ist of t ables table 4.1. product selection guide .............. ................. ................ ................. ................ ..........15 table 1. top marking explanation ....... ................ ................. .............. .............. .............. .......... 16 table 2. top marking explanation ....... ................ ................. .............. .............. .............. .......... 17 table 7.1. package dimensions .. ............... ................ ................. ................ ................. ............ 22 table 7.2. package dimensions .. ............... ................ ................. ................ ................. ............ 23 table 8.1. 10-pin msop dimensions ........... ................. ................ ................. ................ .......... 25 table 9.1. pcb land pattern dimensions .............. .............. .............. .............. .............. .......... 27 table 10.1. recommended oper ating conditions .......... ................ ................. .............. .......... 28 table 10.2. absolute maximum ratings 1 , 2 ................ ................. ................ ................. ............ 28 table 10.3. dc characteristic s ................ ................ ................ ................. ................ ............... 29 table 10.4. si4010 rf transmitter char acteristics ............. .............. .............. .............. .......... 30 table 10.5. low battery detector char acteristics ......... ................ ................. ................ .......... 31 table 10.6. optional crystal oscillator characteristics .. ............... ................. ................ .......... 31 table 10.7. eeprom characteri stics ................. ................. .............. .............. .............. .......... 32 table 10.8. low power oscillator characteristics .... .............. .............. .............. .............. ........ 32 table 10.9. sleep timer charac teristics ............. ................. .............. .............. .............. .......... 32 table 22.1. cip-51 instruct ion set summary ...... ................. .............. .............. .............. .......... 57 table 24.1. boot xdata status variabl es ................. ................. ................ ................. ............ 76 table 24.2. run chip retest prot ection flags: nvm programmer ......... .............. ........... ........ 81 table 25.1. special function register (sfr) memory m ap ................. .............. .............. ........ 85 table 25.2. special func tion registers ........... ................ ................ ................. .............. .......... 86 table 25.3. xreg register memory map in external memory ............ .............. .............. ........89 table 25.4. xreg regist ers ................. .............. .............. .............. ............... .............. ............ 90 table 26.1. interrupt summary .......... ................ ................ .............. ............... .............. ............ 93 table 30.1. 10?pin mode ...... ................ ................. ................ ................. ................ ............... 109 table 30.2. 14?pin mode ...... ................ ................. ................ ................. ................ ............... 109 table 30.3. gpio special role s .............. ................ ................ ................. ................ ............. 111 table 30.4. gpio special roles cont rol and order .......... .............. ............... .............. .......... 116
SI4010-C2 8 rev. 1.0 l ist of xreg r egisters xreg definition 12.2. wpa_ca p .............. ................ ................. ................ ................. .......... 38 xreg definition 12.3. bpa_tr im ............ ................ ................ ................. ................ ............. 39 xreg definition 15.1. blposc_trim . .............. .............. .............. ............... .............. .......... 47 xreg definition 16.1. bxo_ct rl ........... ................ ................ ................. ................ ............. 49 xreg definition 17.3. ifc_co unt ........... ................ ................. ................ ................. .......... 53 xreg definition 23.1. abmtp_rdata[16] ............. ................ ................. ................ ............. 68
SI4010-C2 9 rev. 1.0 l ist of sfr r egisters sfr definition 12.1. pa_lvl .. ................. ................ ................ ................. ................ ............... 38 sfr definition 13.1. ods_ctrl ............... ................ ................. ................ ................. ............ 41 sfr definition 13.2. ods_timi ng ................. ................ ................ ................. .............. ..........42 sfr definition 13.3. ods_data ............... ................ ................. ................ ................. ............ 43 sfr definition 13.4. ods_rate l ............. ................ ................. ................ ................. ............ 43 sfr definition 13.5. ods_rate h .............. ................. ................ ................. ................ ..........44 sfr definition 13.6. ods_warm 1 ............. ................. ................ ................. ................ .......... 44 sfr definition 13.7. ods_warm 2 ............. ................. ................ ................. ................ .......... 45 sfr definition 14.1. lc_fsk .. ................. ................ ................ ................. ................ ............... 46 sfr definition 15.2. sysgen ... ................ ................ ................. ................ ................. ............48 sfr definition 17.1. fc_ctrl .. ................ ................ ................. ................ ................. ............ 52 sfr definition 17.2. fc_inter val ................... ................. .............. .............. .............. .......... 53 sfr definition 22.1. dpl .... ................ ................ ................. ................ ................. ................ ... 61 sfr definition 22.2. dph .... ................ ................ ................. ................ ................. ................ ... 61 sfr definition 22.3. sp ...... ................ ................ ................. ................ ................. ............... .... 62 sfr definition 22.4. acc .... ................ ................ ................. ................ ................. ................ ... 62 sfr definition 22.5. b ...... ................. ................ ................ ................. ................ ................ ...... 63 sfr definition 22.6. psw ..... ................ ................. ................ ................. ................ ............... ..64 sfr definition 24.2. boot_fla gs ................... ................. .............. .............. .............. .......... 78 nvm byte definition 24.3. pr ot3_ctrl .............. .............. .............. .............. .............. .......... 83 sfr definition 24.4. prot0_ctrl ...... ................. .............. .............. .............. .............. .......... 84 sfr definition 26.1. ie ..... ................. ................ ................ ................. ................ ................ ...... 94 sfr definition 26.2. ip ..... ................. ................ ................ ................. ................ ................ ...... 95 sfr definition 26.3. eie1 ... ................ ................ ................. ................ ................. ................ ...96 sfr definition 26.4. eip1 ... ................ ................ ................. ................ ................. ................ ...97 sfr definition 26.5. int_flags ............... ................ ................. ................ ................. ............ 98 sfr definition 26.6. port_intcfg .... .............. .............. .............. ............... .............. .......... 100 sfr definition 27.1. pcon ................. .............. .............. .............. .............. .............. ............. 1 02 sfr definition 28.1. gfm_data ................. ................. ................ ................. .............. .......... 104 sfr definition 28.2. gfm_cons t ................. ................ ................ ............... .............. ..........104 sfr definition 28.3. sb ox_data ............... ................. ................ ................. .............. .......... 105 sfr definition 28.4. sys_set ................ ................ ................ ................. ................ ............. 105 sfr definition 30.1. p0 .... ................. ................ ................ ................. ................ ................. ... 118 sfr definition 30.2. p0con ... ................. ................ ................ ................. ................ ............. 11 9 sfr definition 30.3. p1 .... ................. ................ ................ ................. ................ ................. ... 119 sfr definition 30.4. p1con ... ................. ................ ................ ................. ................ ............. 12 0 sfr definition 30.5. p2 .... ................. ................ ................ ................. ................ ................. ... 120 sfr definition 30.6. port_ctr l ............. ................ ................. ................ ................. .......... 121 sfr definition 30.7. port_set ................. ................. ................ ................. .............. .......... 122 sfr definition 31.1. clkout_s et ........... ................ ................. ................ ................. .......... 124 sfr definition 32.1. gpr_ctrl ................. ................. ................ ................. .............. .......... 126 sfr definition 32.2. gpr_data ................. ................. ................ ................. .............. .......... 126 sfr definition 32.3. rbit_dat a .............. ................ ................. ................ ................. .......... 127
SI4010-C2 10 rev. 1.0 sfr definition 33.1. rtc_ctrl ........ ................ .............. .............. ............... .............. .......... 130 sfr definition 34.1. tmr_clkse l ................ ................ ................ ............... .............. .......... 139 sfr definition 34.2. tmr2ctrl ........ ................ .............. .............. ............... .............. .......... 140 sfr definition 34.3. tmr2rl . ................. ................ ................ ................. ................ ............. 142 sfr definition 34.4. tmr2rh ................. ................ ................ ................. ................ .............142 sfr definition 34.5. tmr2l ... ................. ................ ................ ................. ................ ............. 14 3 sfr definition 34.6. tmr2h ... ................. ................ ................ ................. ................ ............. 14 3 sfr definition 34.7. tmr3ctrl ........ ................ .............. .............. ............... .............. .......... 144 sfr definition 34.8. tmr3rl . ................. ................ ................ ................. ................ ............. 146 sfr definition 34.9. tmr3rh ................. ................ ................ ................. ................ .............146 sfr definition 34.10. tmr3l . ................. ................ ................ ................. ................ ............. 147 sfr definition 34.11. tmr3h . ................. ................ ................ ................. ................ ............. 147
rev. 1.0 11 SI4010-C2 1. system overview the si4010 is a fully integrated crystal-less cmos soc rf transmitter with an embedded cip-51 8051 mcu designed for the sub 1 ghz ism frequency bands. th is chip is optimized fo r battery powered applica- tions with operating voltages from 1.8 to 3.6 v and ul tra-low current consumption with a standby current of less than 10 na. the high power amplifier can suppl y up to +10 dbm output power with 19.5 db of pro- grammable range. moreover, the soc transmitter includ es a patented antenna tuning circuit that automati- cally fine tunes the resonance frequency and im pedance matching between the pa output and the connected antenna for optimum transmit efficiency and low harmonic content. fsk and ook modulation is supported with symbol rates up to 100 kbps. like all wi reless devices, users are responsible for complying with applicable local regulatory requirements for radio transmissions. the embedded cip-51 8051 mcu provides the core func tionality of the si4010. user software has com- plete control of all peripherals, and may individually sh ut down any or all peripherals for power savings. a space of 8 kb of on-chip one-time programmable nvm memory is available to store the user program and can also store unique transmit ids. in case of power outages due to battery removal, 128 bi ts of eeprom is available for counter or other operations provid ing non-volatile stor age capability. a library of useful soft- ware functions such as aes encryption, a patented 32 -bit counter providing 1 m cycles of read/write endurance, and many other functions are included in the 12 kb of rom to reduce user design time and code space. general purpose input/ output pins with push bu tton wake-on touch ca pability, a programma- ble system clock, and ultra low power timers are al so available to further reduce current consumption. the si4010 includes silicon laboratories' 2-wire c2 debug and programming inte rface. this debug logic supports memory inspection, viewing and modification of special function registers (sfr), setting break points, single stepping, and run and halt commands. all analog and digital peripherals are fully functional while debugging using c2. the two c2 interface pins can be shared with user func tions, allowing in-system debugging without occupying package pins. the device leverages silicon labs' patented and proven crystal-less oscillator technology and offers better than 150 ppm carrier frequency stabilit y over the temperature range of 0 to + 70 c and 250 ppm carrier frequency stability over the in dustrial range of ?40 to + 85 c without the us e of an external crystal or fre- quency reference. the in ternal mcu automatically calibrates the on-chip volt age controlled oscillator (lcosc) which forms the output carrier frequency for process and temperature variations. an external 1- pin crystal oscillator option is available for applications requir ing tighter frequency tolerances. digital integration reduces the amount of required external components compared to traditional offerings, resulting in a solution that only requires a printed circuit board (p cb) implementation area of approximately 25 by 50 mm (including battery, switches, and 25 mm 2 antenna). the high integration of the si4010 improves the system manufacturing reliability and qu ality and minimizes costs. this chip offers industry leading rf performance, high integr ation, flexibility, low bom, small b oard area, an d ease of design. no production alignment is necessary as all rf functions are integrated into the device.
SI4010-C2 12 rev. 1.0 figure 1.1. si4010 block diagram si4010 sfr bus c2 port contr temp demod ods freq counter cip-51 8051 controller core 256 byte iram 256 byte xreg 4k byte ram 12k byte rom digital peripherals intc rtc tmr 2,3 aes 128b accel gpio0/xtal/vpp gpio1 gpio2 gpio3 gpio4/c2dat gpio5/c2clk/led gpio6 gpio7 gpio8 gpio9 nvm 8 kb eeprom 128-bit memory controller 14p soic package only lcosc pa divider xtal osc hvram 8 byte auto tune fsk ook lposc temp sensor ldo por bandgap va vd txp txm vdd gnd slp tmr rf analog core
rev. 1.0 13 SI4010-C2 2. test circuit figure 2.1. test block diagram with 10-pin msop u1 si4010-gt gpio0 gnd txm txp vdd gpio1 gpio2 gpio3 gpio4 led 1 2 3 4 5 10 9 8 7 6 c1 1 uf tester interface gp1 gp2 gp3 gp4 gp5 test equipment gp0 vdd matching network
SI4010-C2 14 rev. 1.0 3. typical application schematic 3.1. si4010 used in a 5-button rke system with led indicator figure 3.1. si4010 used in a 5-button rke system with led indicator 3.2. si4010 with an external crystal in a 4-button rke system with led indicator figure 3.2. si4010 with an external crystal in a 4-button rke system with led indicator u1 si4010-gt gpi0 gnd txm txp vdd gpio1 gpio2 gpio3 gpio4 led 1 2 3 4 5 10 9 8 7 6 cr2032 coin cell 1.8 to 3.6 v loop a ntenn a c1 1uf sw1 d1 sw0 sw2 sw3 sw4 c2 u1 si4010-gt gpi0 gnd txm txp vdd gpio1 gpio2 gpio3 gpio4 led 1 2 3 4 5 10 9 8 7 6 cr2032 coin cell 1.8 to 3.6 v loop antenna c1 1uf sw1 d1 sw2 sw3 sw4 c2 x1 c3
rev. 1.0 15 SI4010-C2 4. ordering information table 4.1. product selection guide ordering part number 1 mips (peak) nvm (otp) memory (bytes) ram (bytes) embedded rom functions internal data ram (bytes) hvram (bytes) eeprom (bits) 128-bit aes accelerator gpio with wakeup 2 led driver sleep timer +10 dbm rf transmitter ldo with por circuit low battery detector automotive qualified 3 lead-free (rohs compliant) package SI4010-C2-gt 24 8k 4k y 256 8 128 y 5 1yyyy ? y msop-10 SI4010-C2-gs 24 8k 4k y 256 8 128 y 9 1yyyy ? y soic-14 SI4010-C2-at 24 8k 4k y 256 8 128 y 5 1yyyy y y msop-10 SI4010-C2-as 24 8k 4k y 256 8 128 y 9 1yyyy y y soic-14 notes: 1. add an ?(r)? at the end of the device part number to denote tape and reel option. 2. assumes led driver is used and no external crystal. 3. aec q100 qualification is pending.
SI4010-C2 16 rev. 1.0 5. top markings 5.1. soic figure 1. si4010 top marking table 1. top marking explanation line characters description line 1 circle = 1.1 mm diameter left-justified "e3" pb-free symbol customer part number si4010c2 line 2 yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the assembly date. tttttt = trace code manufacturing code characters from the markings section of the assembly purchase order form. ?
rev. 1.0 17 SI4010-C2 5.2. msop figure 2. si4010 top marking table 2. top marking explanation line characters description line 1 device part number 10c2 line 2 tttt = trace code line 2 from the "markings" section of the assembly purchase order form. line 3 yww = date code date code assigned by the assembly house. y = last digit of current year (ex: 2008 = 8) ww = work week of mold date. ?
SI4010-C2 18 rev. 1.0 6. pin definitions 6.1. msop, application pin number(s) name description 1 gpio0/xtal general purpose input pin. can be configured as an input pin for a crystal. 2 gnd ground. connect to ground plane on pcb. 3, 4 txm, txp transmitter differential outputs. 5 vdd power. 6 led dedicated led driver. 7, 8, 9, 10 gpio[4:1] general purpose input/output pins. gpio0/xtal si4010-gt 2 3 6 7 8 4 5 9gpio2 gpio3 gpio4 led vdd txp gnd txm 1 10 gpio1
rev. 1.0 19 SI4010-C2 6.2. msop, programming/debug mode pin number(s) name description 1 vpp +6.5 v required for nvm (otp) memory programming. 2gnd ground. connect to ground plane on pcb. 3txm transmitter differential output. 4txp transmitter differential output. 5vdd power. 6 c2clk c2 clock interface. 7c2dat c2 data input/output pin. 8, 9, 10 gpio[3:1] general purpose input/output pins. vpp/gpio0/xtal si4010-gt 2 3 6 7 8 4 5 9gpio2 gpio3 c2dat/gpio4 c2clk/led vdd txp gnd txm 1 10 gpio1
SI4010-C2 20 rev. 1.0 6.3. soic package, application pin number(s) name description 1 gpio9 general purpose input/output pin 2 gpio0/xtal general purpose input pin. can be configured as an input pin for a crystal 3 gnd ground. connect to ground plane on pcb 4,5 txm, txp transmitter differential outputs 6vddpower 7,8 gpio[7:6] general purpose input/output pins 9 led dedicated led driver 10,11,12,13 gpio[4:1] general purpose input/output pins 14 gpio8 general purpose input/output pin si4010-gs 3 4 9 10 11 5 6 12 gpio2 gpio3 gpio4 led vdd gpio0/xtal txp gnd txm 2 13 gpio1 gpio9 1 14 gpio8 8 7gpio6 gpio7
rev. 1.0 21 SI4010-C2 6.4. soic package, programming/debug mode pin number(s) name description 1 gpio9 general purpose input/output pin 2 vpp +6.5 v required for nvm (otp) memory programming 3 gnd ground. connect to ground plane on pcb 4,5 txm, txp transmitter differential outputs 6vddpower 7,8 gpio[7:6] general purpose input/output pins 9 c2clk c2 clock interface 10 c2dat c2 data input/output pin 11,12,13 gpio[4:1] general purpose input/output pins 14 gpio8 general purpose input/output pin si4010-gs 3 4 9 10 11 5 6 12 gpio2 gpio3 c2dat/gpio4 c2clk/led vdd vpp/gpio0/xtal txp gnd txm 2 13 gpio1 gpio9 1 14 gpio8 8 7gpio6 gpio7
SI4010-C2 22 rev. 1.0 7. package specifications 7.1. 10-pin msop figure 7.1 illustrates the package de tails for the si40 10, 10-pin msop package. table 7.1 lists the values for the dimensions shown in the illustration. figure 7.1. 10-pin msop package table 7.1. package dimensions symbol millimeters symbol millimeters min nom max min nom max a ? ? 1.10 e 0.50 bsc a1 0.00 ? 0.15 l 0.40 0.60 0.80 a2 0.75 0.85 0.95 l2 0.25 bsc b 0.17 ? 0.33 q 0 ? 8 c 0.08 ? 0.23 aaa ? ? 0.20 d 3.00 bsc bbb ? ? 0.25 e 4.90 bsc ccc ? ? 0.10 e1 3.00 bsc ddd ? ? 0.08 notes: 1. all dimensions are shown in millimeters (mm). 2. dimensioning and tolerancing per asme y14.5m-1994. 3. this drawing conforms to jedec outline mo-187, variation ?ba.? 4. recommended card reflow profile is per the jedec/ip c j-std-020 specification for small body components.
rev. 1.0 23 SI4010-C2 7.2. 14-pin soic package figure 7.2 illustrates the package deta ils for the si4010, 14-p in soic package. table 7.2 lists the values for the dimensions shown in the illustration. figure 7.2. 14-pin soic package table 7.2. package dimensions symbol min max symbol min max a ? 1.75 l 0.40 1.27 a1 0.10 0.25 l2 0.25 bsc b 0.33 0.51 q 0 8 c 0.17 0.25 aaa 0.10 d 8.65 bsc bbb 0.20 e 6.00 bsc ccc 0.10 e1 3.90 bsc ddd 0.25 e 1.27 bsc notes: 1. all dimensions are sh own in millimeters (mm). 2. dimensioning and tolerancing per asme y14.5m-1994. 3. this drawing conforms to jede c outline ms012, variation ab.? 4. recommended card reflow profile is per the jedec/ipc j-std-02 0 specification for small body components.
SI4010-C2 24 rev. 1.0 8. pcb land pattern 10-pin msop figure 8.1. 10-pin msop recommended pcb land pattern
rev. 1.0 25 SI4010-C2 table 8.1. 10-pin msop dimensions dimension min max c1 4.40 ref e 0.50 bsc g1 3.00 ? x1 ? 0.30 y1 1.40 ref z1 ? 5.80 notes: general 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per asme y14.5m-1994. 3. this land pattern design is based on the ipc-7351 guidelines. 4. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05mm. solder mask design 1. all metal pads are to be non-sol der mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1. card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow prof ile is per the jedec/ipc j-std- 020 specification for small body components.
SI4010-C2 26 rev. 1.0 9. pcb land pattern 14-pin soic package figure 9.1. 14-pin soic recommended pcb land pattern ?
rev. 1.0 27 SI4010-C2 table 9.1. pcb land pattern dimensions dimension min max c1 5.30 5.40 e 1.27 bsc x1 0.50 0.60 y1 1.45 1.55 notes: general 1. all dimensions shown are in m illimeters (mm) unless otherwise noted. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 1. all metal pads are to be non-sol der mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 1. a stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. the stencil thickness should be 0.125 mm (5 mils). 3. the ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. card assembly 1. a no-clean, type-3 solder paste is recommended. 2. the recommended card reflow prof ile is per the jedec/ipc j-std- 020 specification for small body components.
SI4010-C2 28 rev. 1.0 10. electrical characteristics table 10.1. recommended operating conditions parameter symbol test condition min typ max unit supply voltage v dd 1.8 ? 3.6 v supply voltage slew rate initia l battery insertion* 20 ? 650 mv/ us ambient temperature t a ?40 25 85 c digital input range digital input signals ?0.3 ? v dd + 0.3 v *note: recommend bypass capacitor = 1 f; slew rate measured 1 v < v dd ,< 1.7 v. table 10.2. absolute maximum ratings 1,2 parameter symbol value unit supply voltage v dd ?0.5 to 3.9 v input current 3 i in 10 ma input voltage 4 v in ?0.3 to (v dd + 0.3) v junction temperature t j ?40 to 90 ? c storage temperature t stg ?55 to 150 ? c notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure beyond recommended operating conditions for extended periods may affect device reliability. 2. handling and assembly of these devices should only be done at esd-protected workstations. 3. all input pins besides v dd . 4. for gpio pins configured as inputs.
rev. 1.0 29 SI4010-C2 table 10.3. dc characteristics (ta = 25 c, vdd = 3.3 v, rl = 480 ?? , unless otherwise noted) parameter symbol test condition min typ max unit supply current 1 i vdd +10 dbm output, ook, manchester ? 14.2 ? ma +6.5 dbm output, ook, manchester ? 11.3 ? ma +10 dbm, fsk ? 19.8 ? ma +6.5 dbm output, fsk ? 14.1 ? ma sleep timer mode i st only sleep timer is enabled ? 700 ? na standby supply current i sb all gpio floating or held high ? 10 ? na led sink current i led v out > 200 mv ? 0.68 ? ma gpio[0-9] pull up ? resistance r pu 48 55 62 k ? high level input voltage 2 v ih trip point at 0.45 x v dd 0.506 x v dd v low level input voltage 2 v il trip point at 0.45 x v dd 0.42 x v dd v high level input current 2 i ih v in = v dd ?? 10a low level input current 2 i il v in = 0 ? ? 10 a high level output voltage 3 v oh i source = 500 a 3.0 ? ? v low level output voltage 3 v ol i sink = 500 a ? ? 0.3 v notes: 1. tested at 100 mhz carrier. 2. for gpio pins configured as inputs. pullup resistor disabled. 3. for gpio pins configured as outputs.
SI4010-C2 30 rev. 1.0 table 10.4. si4010 rf transmitter characteristics (ta = 25 c, vdd = 3.3 v, rl = 480 ?? ,, soic package unless otherwise noted) parameter symbol test condition min typ max unit frequency range 1 f rf 27 ? 960 mhz frequency noise (rms) 2 allen deviation, measured across 1 ms interval ?0.3 ?ppm phase noise @ 915 mhz 10 khz offset ? ?70 ? dbc/hz 100 khz offset ? ?100 ? dbc/hz 1 mhz offset ? ?105 ? dbc/hz frequency tuning time ? 5 ? ms carrier frequency accuracy 0 c t a 70 c ?150 ? +150 ppm ?40 c t a 85 c ?250 ? +250 ppm frequency error contribution with external crystal ?10 ? +10 ppm transmit power 3 maximum programmed tx power, with optimum differen- tial load, v dd > 2.2 v ? 10 ? dbm minimum programmed tx power, with optimum differen- tial load, v dd > 2.2 v ??13 ?dbm power variation vs temp and supply, with optimum differential load, v dd > 2.2 v ?1.0 ? 0.5 db power variation vs temp and supply, with optimum differential load, v dd > 1.8 v ?2.5 ? 0.5 db transmit power step size from ?13 to 10 dbm ?0.25 ? db pa edge ramp rate programmable range ook mode 0.34 ? 10.7 us data rate ook, manchester encoding 0.1 ? 50 kbaud fsk, nrz encoding 0.1 ? 100 kbaud notes: 1. the frequency range is continuo us over the specified range. 2. the frequency step size is lim ited by the frequency noise. 3. optimum differential load is equal to 3.5 v/(11.5 ma/2 x 4/pi) = 480 ??? therefore the antenna load resistance in parallel with the si4010 differential output resistance should equal 480 ??? 4. total nvm copy time = 2 ms + (nvm copy boot time per kb) x (nvm data in kb).
rev. 1.0 31 SI4010-C2 peak to peak ? fsk deviation max frequency deviation ? 275 ? ppm deviation resolution ? 2 ? ppm deviation accuracy (4 ppm + 2% pk-pk target fsk deviation in ppm) ppm ook modulation depth 60 ? ? db antenna tuning capaci- tive range (differential) 315 mhz 2.4 ? 12.5 pf nvm copy boot time ? per kb 4 ?3.6 ?ms/ kb table 10.5. low battery detector characteristics (ta = 25 c, vdd = 3.3 v, rl = 480 ?? , unless otherwise noted) parameter symbol test condition min typ max unit battery voltage measurement accuracy ?2 ?% table 10.6. optional crystal oscillator characteristics (ta = 25 c, vdd = 3.3 v, rl = 480 ?? , unless otherwise noted) parameter symbol test condition min typ max unit crystal frequency range gpio0 configured as crystal oscillator 10 ? 13 mhz input capacitance (gpio0) gpio0 configured as a crystal oscillator; xo_lowcap=1 ?3 ?pf gpio0 configured as a crystal oscillator; xo_lowcap=0 ?5.5 ?pf crystal esr gpio0 configured as a crystal oscillator; xo_lowcap=1 ??120 ? gpio0 configured as a crystal oscillator; xo_lowcap=0 ?? 80 ? start-up time gpi00 configured as a crystal oscillator; crystal at max esr ?9 50ms table 10.4. si4010 rf transmitter characteristics(continued) (ta = 25 c, vdd = 3.3 v, rl = 480 ?? ,, soic package unless otherwise noted) parameter symbol test condition min typ max unit notes: 1. the frequency range is continuo us over the specified range. 2. the frequency step size is lim ited by the frequency noise. 3. optimum differential load is equal to 3.5 v/(11.5 ma/2 x 4/pi) = 480 ??? therefore the antenna load resistance in parallel with the si4010 differential output resistance should equal 480 ??? 4. total nvm copy time = 2 ms + (nvm copy boot time per kb) x (nvm data in kb).
SI4010-C2 32 rev. 1.0 table 10.7. eeprom characteristics parameter conditions min typ max units program time independent of number of bits changing values ?840ms count per 32-bit counter using api ? 1000000 1000100 cycles write endurance (per bit)* 50000 ? ? cycles note: *api uses coding technique to achieve write endurance of 1m cycles per bit. table 10.8. low power oscillator characteristics v dd = 1.8 to 3.6 v; t a = ?40 to +85 c unless otherwise spec ified. use factory-calibrated settings. parameter conditions min typ max units programmable frequency range programmable divider in powers of 2 up to 128 .1875 ? 24 mhz frequency accuracy ?1 ? +1 % table 10.9. sleep timer characteristics v dd = 1.8 to 3.6 v; t a = ?40 to +85 c unless otherwise spec ified. use factory-calibrated settings. parameter conditions min typ max units maximum programmable time ? ? 6800 s time accuracy using api to program timer ?1.5 ? 1.5 %
rev. 1.0 33 SI4010-C2 11. system description figure 11.1. functional block diagram 11.1. overview the si4010 is a fully integrated crystal-less cmos soc rf transmitter with an embedded cip-51 8051 mcu as the core processor of the system. the device is designed for low power battery applications with standby currents of less than 10 na to optimize ba ttery life. upon power up, t he device immediately enters standby mode. in this mode, all blocks are powered down except for the low leakage high-voltage ram (hvram) which provides 8 bytes of me mory that retains its state as long as the battery voltage is applied and above 1.8 v. the si4010 is aw akened from standby mo de by a falling edge to ground on any one of the gpio pins. in addition, the si4010 has a low-powe r sleep timer for applications where the device is required to wake up and pe riodically check for events instead of being wakened by a gpio falling edge. upon wake up, the boot loader copies data from the one time programmable (otp) nvm to code/xdata ram (4 kb) because the mcu can only operate with programs stored in ram or rom. the copy process occurs on each wake-up event and requires approximately 2 ms of fixed time plus 3.6 ms per kb of data or 16.4 ms to fill the full 4 kb of code/xdata ram. af ter the nvm boot copy proce ss is completed, the mcu runs the user program in ram and can also run functions from rom that are called by the user program such as button service routines to facilitate button debouncing, button time stamps , etc. a complete list and detailed description of all the api functions is given in application note ?an370: si4010 software program- ming guide.? si4010 sfr bus c2 port contr temp demod ods freq counter cip-51 8051 controller core 256 byte iram 256 byte xreg 4k byte ram 12k byte rom digital peripherals intc rtc tmr 2,3 aes 128b accel gpio0/xtal/vpp gpio1 gpio2 gpio3 gpio4/c2dat gpio5/c2clk/led gpio6 gpio7 gpio8 gpio9 nvm 8 kb eeprom 128-bit memory controller 14p soic package only lcosc pa divider xtal osc hvram 8 byte auto tune fsk ook lposc temp sensor ldo por bandgap va vd txp txm vdd gnd slp tmr rf analog core
SI4010-C2 34 rev. 1.0 the si4010 has three timing sources. the lcosc is t he most accurate timing s ource native to the chip. each device is factory trimmed and programmed at silicon l abs to produce a frequency accuracy of better than 150 ppm over the temperature range of 0 to + 70 c and 250 ppm over the industrial range of ?40 to +85 c. the lcosc is fitted to a multiple-degree polynomial to compensate for temperature variations both from the on-chip power amplifie r (pa) and also from the external environment. this lcosc oscillates around 3.9 ghz and provides the clock (via the di vider) used to modulate the pa for ook and fsk transmission. the low power oscillator (lposc) is the second timing sour ce and operates at 24 mhz. the lposc is always the source of clocking for the mcu and is turned off only in standby mode. the system clock is programmable allowing the mcu to operate with lower clock frequenc ies while waiting between packets to save power. the rtc and timers 2 and 3 ar e derived from the lposc. the last clock source is the crystal oscillator (xtalosc). this crystal oscillator is unused in ma ny customer applications and used only when a highly accurate carrier frequency is desire d. when enabled, it is us ed before the beginning of a transmission to corr ect the frequency of the lcosc and is then shutdown to save power. an internal fre- quency counter is implemented in hardware to allow for quick frequency ratio measurements to calibrate the different clock sources. the high efficiency pa is a cmos open drain output driv er capable of producing 3.5 vpk differential output swing with a supply voltage of 2.2 v or higher. the pa output has 2.4 to 12.5 pf of differential variable capacitance that is automatically adjusted to resonate the antenna at the start of each packet transmission. this automatic adjustment is realized with a firmware algorithm in the rom and some additional hardware in the pa. maximum power can be transferred to the in ductive antenna load when the antenna and output driver are at resonance and the real component of the load is equal to the optimum load resistance of v pk /(4/pi x i tail /2) where v pk is the peak differential voltage and i tail is the tail current of the pa. at higher resistances the pa is voltage limited and at lower resi stances the pa is current limited. the pa tail current is programmable from 810 ua up to 7.67 ma in 0.25 db steps and there is a boost current bit that multiplies the tail current by 1.5 times allowing it to go up to 11.5 ma. with an antenna load resistance of about 500 ? an output power of +10 dbm is achiev able. edge rate control is also included for ook mode to reduce har- monics that may otherwise violate government regulations. the on-chip temperature sensor (temp sensor) measures the internal temperature of the chip and tem- perature demodulator (temp demod) converts the temp sensors? output into a binary number repre- senting temperature and is used to compensate the frequency of the lcosc when the temperature changes. each device's freque ncy response versus temperatur e is calibrated in the factory. the output data serializer (ods) is responsible for synchronizing the output data to the required data rate and maintaining a steady data flow when data is available. this block produces the edge rate control for the pa in ook mode and the frequency deviation in fsk mode. the block also schedules the power on/off times of the lcosc, divider, and pa to co nserve battery power during transmission. power management is provided on chip with low-drop-out (ldo) regulators for the internal analog and dig- ital supplies, va and vd, respective ly. the power-on reset (por) circuit monitors the power applied to the chip and generates a reset signal to set the chip into a known state. the bandgap produces voltage and current references for the analog blocks in the chip a nd can be shut down when the analog blocks are not used. the embedded cip-51 8051 mcu provides the core func tionality of the si4010. user software has com- plete control of all peripherals, and may individually sh ut down any or all peripherals for power savings. 8k bytes of on-chip one-time programmable nvm memory is available to store the user program and can also store unique transmit ids. 128 bits of eeprom is ava ilable for counter or other operations providing non- volatile storage capability in case of power outages due to battery remo val. a library of useful software functions such as aes encryption, a patented 32-bit co unter providing 1m cycles of read/write endurance, and many other functions are included in the 12 kb of rom to reduce user design time and code space. general purpose in put/output pins with push bu tton wake-on touch capabilit y are available to further reduce current consumption.
rev. 1.0 35 SI4010-C2 the si4010 includes silicon laboratories' 2-wire c2 debug and programming inte rface. this debug logic supports inspection memory, viewing and modification of special function regi sters (sfr), setting break points, single stepping, and run and halt commands. all analog and digital peripherals are fully functional while debugging using c2. the two c2 interface pins can be shared with user func tions, allowing in-system debugging without occupying package pins. 11.2. setting basic si 4010 transmit parameters the basic transmit parameters such as output power, modulation type, data rate, and operating frequency are set by using applications programming interfac e (api) function commands. when using these func- tions certain parameters can be dete rmined by using a calculator spread sheet.the calculator spreadsheet is available through the silicon labs website (www.s ilabs.com) in the support/document library/ezradio section, and it is part of each si4010 development kit. consult ?an547: si4010 calculator spreadsheet usage? for details of the calculator operations. 11.3. applications program ming interface (api) commands the api implements several dozen functions. the user can build an application using these api functions. see ?an370: si4010 software programming guide? for more details.
SI4010-C2 36 rev. 1.0 12. power amplifier figure 12.1. simplified pa block diagram the cmos power amplifier (pa) is a differential open drain amplifier capable of delivering +10 dbm of out- put power. maximum power can be transferred to an inductive antenna load when the antenna and output driver of the pa are at resonance and the real comp onent of the combined load is equal to the optimum load resistance of v pk /(4/pi x i tail /2) where v pk is the peak differential voltage of the pa and i tail is the tail current of the pa. this optimum load resistance is th e parallel combination of the pa output resistance and the differential antenna resistance. at higher resistan ces the pa is voltage limited and at lower resistances the pa is current limited. the pa tail current is programmable from 810 a up to 7.67 ma (sfr register pa_lvl) in 0.25 db steps and there is a boost cu rrent bit (xreg pa_trim.pa_max_drv) that multiplies the tail current by 1.5 times allowing it to go up to 11.5ma. the maximum differential peak-to-peak voltage is 3.5 v when the supply is 2.2 to 3.6 v and drop s linearly down to 3.0 v when the supply is at 1.8 v the calculator spreadsheet tool computes the requ ired antenna impedance and api settings to achieve the user desired output power. proper layout and matchi ng techniques are all necessary to ensure optimal performance. figure 9.1 shows a typi cal application schematic of the si4010 for a differential loop antenna. application note "an369: antenna interface for the si401x transmitters" provides detailed infor- mation about designing the antenna inte rface for the si401x transmitters. with proper filtering and layout techniques, the si4010 can conform to us fcc part 15.231 and european en 300 220 regulations. edge rate control is also included for ook mode to reduce harmonics that may othe rwise violate government regulations. edge shaping is accomplished by gradually turning on and off the driver transistors of the pa. the edge shaping parameters are controlled by the od s block and is automatically determined by the cal- culator spread sheet based on the desired data rate and encoding method. users must comply with local radio frequency transmission regulations. off-chip capacitor tolerances, loop antenna manufactu ring tolerances, and environmental variations can lead to impedance mismatch at the pa output causing reduced radiated power level. the si4010 includes an automatic antenna tuning circuit to reduce the mism atch by adjusting the on-chip variable capacitor to resonate with the inductance of the antenna. the pa ou tput has 2.4 to 12.5 pf of variable capacitance that is adjusted to tune the antenna to the correct frequency using a firmw are assisted algorithm and on-chip hardware.the variable capacitance is adjusted at the start of each packet transmission during the pream- ble. the switching network in the capacitor array is compensated over process, voltage, and temperature i tail feedback (hw, sw) frequency tune, const pwr pa txp input txm
rev. 1.0 37 SI4010-C2 (pvt) to keep its quality factor (q) nearly constant at 50 (at 434 mhz). the starting value of the 9-bit capacitor word (xreg pa_cap) is chosen with the help of the calculator spreadsheet. in general, a high operating frequency requires a smaller capacitance and hence a low value capacitive word. the output resistance of the pa is a strong f unction of the capacitive word bec ause the variable capacitor is imple- mented with a capacitor and a mos switch. when more capacitance is turned on (higher capacitive word), more switches turn on and with a constant q design, the output resistance of the pa decreases and has more loss. thus another consideration for the nominal capacitive word besides the operating frequency is how the resistive loading of the varactor affects th e optimum load resistance and the required antenna resistance. the calculator illustrate s how the nominal value of the capa citive word affects the desired antenna resistance. in addition to the algorithm used to tune the antenna for resonance, a software control loop using the power amplifier module api can keep the transmit radiat ed power constant due to changes in temperature and/or capacitance of the antenna. for example, if ch anges in the temperature of the transmitter and/or the capacitance of the antenna cause the impedance of the load (the parallel combination of the pa and antenna resistances) to dec rease, this will cause a decr ease in the output voltage of the pa and hence the radiated power. both the operating temperature and th e capacitor tuning word are monitored by the chip and may be used to increase the nominal drive current to bring the product of the output voltage and driver capacitance back to what it was prior to the environm ental change. in order for this loop to operate cor- rectly, the parameters alpha and beta need to be determined from measured antenna characteristics. alpha represents the required change in blevel (the nominal power level programmed through the api interface) given changes in temperature. beta repres ents the required change in blevel given changes in programmed driver capacitance. remember that each lsb change in blevel corresponds to a 0.25 dbm change in power. for example, if experimental me asurement shows that the radiated power changes by 1 dbm over a 50 c change in temperature, alpha would be set to 4/50=0.08. in this alpha equation, the 4 is derived from 1 dbm/0.25 dbm per step in bleve l. thus, the units of alpha are (lsb steps in blevel)/(change in temp). beta can be determined using the si4010 calculator spreadsheet. these two parameters should be entered as parameters to the api to provide accurate adjustments to the radiated power. in addition to these parameters, the differential peak voltage and current drive of the pa should not be maximized prior to using this loop so adjustments in the current drive, which affects the differential peak voltage, can be made by the feedback loop. if either the current or voltage is maximized prior to using the loop, the loop would not be able to further adjust the current or voltage and hence fail to operate properly. see ?an547: si4010 calculator spreadsheet usage? for more details.
SI4010-C2 38 rev. 1.0 12.1. register description sfr address = 0xce xreg address = 0x400c sfr definition 12.1. pa_lvl bit76543210 name pa_lvl_nslice[4:0] pa_lvl_bias[2:0] type r/w r/w reset 00 bit name function 7:3 pa_lvl_ nslice [4:0] number of slices enabled in the pa driver. this parameter determines the output cu rrent drive of the pa. programming this register directly is not recommended. use the vpa_setup() api function instead. 2:0 pa_lvl_ bias [2:0] pa level bias. this parameter determines the bias current per slice of the pa. programming this register directly is not recommended. use the vpa_setup() api function instead. xreg definition 12.2. wpa_cap byte offset 10 name pa_cap[1:0] type r/w reset 0x00 0x00 bit name function 1:0 pa_cap [1:0] pa variable capacitance. 9-bit linear control value of the output capacitance of the pa. accessed as 2 bytes (word) in big-endian fashion. upper bits [15: 9] are read as 0. r ange: 2.4?12.5 pf (not exact values). the resonance frequency and impedance matching between the pa output and the connecte d antenna can be tuned by changing this value. this register is set by the power amplifier module api.
rev. 1.0 39 SI4010-C2 xreg address = 0x4012 xreg definition 12.3. bpa_trim bit76543210 name pa_max_ drv reserved reserved reserved reserved type r/w reset 0 bit name function 7:5 unused 4 pa_max_ drv pa max drive bit. this parameter boost the bias current of the pa by 1.5 times up to 10.5 ma. the values entered into this register come fr om the power amplifier module api. this bit should be set without changing the other bits. 3:0 reserved reserved.
SI4010-C2 40 rev. 1.0 13. output data serializer (ods) 13.1. description the ods block is responsible for synchronizing the out put data to the required data rate and maintaining a steady data flow during transmission. the serializer accomplishes the following functions: ? controls the edge rate of the pa on/off transitions. ? schedules pa, divider, lcosc on/off power transitions for minimal power consumption. ? controls the serial data rate. ? provides handshake interface and a 1 byte pipeline to allow a software process to maintain steady dataflow. ? modulates a 7 bit ?frequency deviation? bus to the lc oscillator to allow for fsk operation. ? provides test features to force on the power state of the lcosc, divider, and pa; recirculating a fixed pattern; forcing the f sk offset frequency. the sfr and xreg settings of this block are determined from the desired modulation, data rate, and encoding method and are automatically set by the od s api in conjunction with the calculator. users are recommended to use the ods api module functions for setting these registers. 13.2. timing figure 13.1. ook timing example figure 13.2. fsk timing example pa_lvl_nslice[4:0] lc_ena lc_w arm up div_ena div_warmup pa_ena pa_w armup symbol time edge time (co f f fos) pa_lvl_nslice[4:0] lc_ena div_ena pa_ena fsk_shift[6:0]
rev. 1.0 41 SI4010-C2 13.3. register description sfr address = 0xa9 sfr definition 13.1. ods_ctrl bit76543210 name ods_shift_ctrl [1:0] fsk_for ce_dev fsk_ mode force_ lc force_ div force_ pa ods_en type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:6 ods_ shift_ ctrl[1:0] ods output control on last bit. controls behavior of serializer when data runs out. 00: the pa, divider, and lcosc shutdown after last bit. 01: reuse the last symbol group for transmission. 10: all 0s data. 11: all 1s data. 5 fsk_ force_ dev force fsk deviation. 0: normal operation. 1: force the lcosc to frequency deviate regardless of data pattern or fsk_mode. 4fsk_mode selects modulation mode. 0: ook mode. 1: fsk mode. 3force_lc force lcosc on. .0: normal operation. 1: force lscosc on. 2 forc_div force divider on. .0: normal operation. 1: force divider on. 1force_pa force pa on. .0: normal operation. 1: force pa on. in addition, pa_lvl_nslice[4:0] in pa_lvl register is passed directly through the serializer, unchanged. 0ods_en enable the serializer. 0: disable the ods. 1: enable the ods.
SI4010-C2 42 rev. 1.0 sfr address = 0xaa sfr definition 13.2. ods_timing bit76543210 name ods_group_width[2:0] ods_edge_time [1:0] ods_ck_div[2:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:5 ods_ group_ width[2:0] controls symbol group width, from 2?8 symbols. set to 4 to transmit 5 symbol groups obtained from 4/5 encoding. or set to 7 to send 8 symbol group obtained from manchester encoding of 4 bits. note that ods_group_width can be changed dynamically prior to writing the ods_data regis- ter, should you want to (for example) add 2 more symbols to the end of a ? transmission which was previously using 8 symbol groups. 4:3 ods_ edge_ time [1:0] controls pa edge time. additional division factor in range 1-4 (ods_edge time+1). edge rate: 8 x (ods_ck_div+1)*(ods_edge_time+1)/24 mhz. when clk_ods is in range of 3- 8 mhz, edge rate can be selected from 1us to 10.7 s. study has indicated that in the worst case (20 kbps manchester), edge rates somewhat higher than 4 s are needed. 2:0 ods_ck_ div[2:0] controls the clock of the ods. sets the division factor of the 24 mhz system clock to produce clk for the ods mod- ule. division factors are 1?8 (ods_ck_div+1). generally should select factor which produces serializer clock in range of ~ 3-8 mhz. using the si4010 calculator spreadsheet in order to determine the correct value of this parameter is strongly recommended .
rev. 1.0 43 SI4010-C2 sfr address = 0xab sfr address = 0xac sfr definition 13.3. ods_data bit76543210 name ods_data[7:0] type r/w reset 00000000 bit name function 7:0 ods_data [7:0] ods input data. symbol group register. side effect of writin g is clearing of ods_empty flag. it gener- ates a single pulse for the ods to notify the tx ods data sfr holding register been written to and contains new data. the pulse is a registered write pu lse, so it will be generated when the data is stable in the holding register. ods data format is little endian. sfr definition 13.4. ods_ratel bit76543210 name ods_ratel[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 ods_ratel [7:0] lower byte of the 15-bit wide ods data rate field. symbol rate produced by the serializer is 24mhz/(ods_datarate*(ods_ck_div+1))
SI4010-C2 44 rev. 1.0 sfr address = 0xad sfr address = 0xae sfr definition 13.5. ods_rateh bit76543210 name reserved ods_rateh[6:0] type r r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 reserved read as 0. write has no effect. 6:0 ods_ rateh [6:0] upper bits of 15-bit ods data rate field. see the ods_ratel for description of the serializer data rates. sfr definition 13.6. ods_warm1 bit76543210 name ods_warm_div[3:0] ods_warm_pa[3:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:4 ods_ warm_ div[3:0] sets warm-up time for divider. sets the "warm up" interval for the divider, where it is biased up prior to transmis- sion or on the transition from ook zero bi t to ook one bit. set this value in a way that the warm-up interval of the divider should be 5us for a given ods clock rate. interval is in 4 x clk_ods cycles resolution interval = 4 x ods_warm_div x (ods_ck_div+1)/24 mhz using the si4010 calculator spreadsheet in order to determine the correct value of this parameter is strongly recommended . 3:0 ods_ warm_ pa[3:0] sets warm-up time for pa. sets the "warm up" interval for the pa, where it is biased up prio r to transmission or on the transition from ook zero bit to ook one bit. set this value in a way that the warm-up interval of the pa should be 1us for a given ods clock rate. interval is directly in clk_ods cycles. interval = ods_warm_pa x (ods_ck_div+1)/24 mhz using the si4010 calculator spreadsheet in order to determine the correct value of this parameter is strongly recommended .
rev. 1.0 45 SI4010-C2 sfr address = 0xaf sfr definition 13.7. ods_warm2 bit76543210 name reserved ods_warm_lc[3:0] type rr/w reset 00000000 bit name function 7:4 reserved read as 0x0. write has no effect. 3:0 ods_ warm_ lc[3:0] sets warm-up time for the lcosc. sets the "warm up" interval for the lc o scillator, where it is biased up prior to ? transmission or on the transition from ook zero bit to ook one bit. set this value in a way that the warm-up interval of the lcosc should be 125 s for a given ods clock rate. interval is in 64 x clk_ods cycles resolution interval = 64 x ods_warm_lc x (ods_ck_div+1)/24 mhz using the si4010 calculator spreadsheet in order to determine the correct value of this parameter is strongly recommended .
SI4010-C2 46 rev. 1.0 14. lc oscillator (lcosc) the si4010 vco is a fully integrat ed cmos lc oscillator that operate s at approximatel y 3.9 ghz. this block in conjunction with a programmable frequency di vider generates the transmit carrier frequency. the technology behind the vco is based on the silicon l aboratories si500 crystal- less oscillator chip and forms the core of the si4010s' crystal-less operation. after this device is fact ory trimmed, the vco fre- quency is the most accura te frequency on the chip and sets the ch ips transmit frequency stability unless an external crystal oscillator is used. the device achiev es 150 ppm frequency stab ility over the commercial temperature range of 0 to 70 c and 250 ppm frequency stability over the industrial temp erature range of ?40 to 85 c. the transmit carrier frequency is set by using t he api functions vfcast_tune (desired carrier) and vfcast_setup(). for fsk modulation, the frequency devi ation is also a parameter to the freq_adjustment function. users are recommended to use the api fu nctions to set the corresponding sfr registers. 14.1. register description sfr address = 0xe4 sfr definition 14.1. lc_fsk bit7 6543210 name reserved fsk_deviation[6:0] type r/w r/w reset 0 0000000 bit name function 7 reserved programming this register directly is no t recommended. use the vfcast_fskadj() api function instead. 6:0 fsk_ deviation [6:0] fsk deviation. these bits determine the fsk deviation. prog ramming this register directly is not rec- ommended. use the vfcast_fskadj() api function instead.
rev. 1.0 47 SI4010-C2 15. low power oscillator an d system clock generator the source of all digital system clocks is derived from the low power oscillator (lposc) and system clock generator. the lposc produces a 24 mhz clock signal and is used by the system clock generator to pro- duce the system clock. this system clock is applied to all digital blocks including the mcu and is program- mable via the sysgen sfr register which is useful for power savings. users ar e recommended to use the system module function api to set the registers. 15.1. register description xreg address = 0x4002 xreg definition 15.1. blposc_trim bit76543210 name lposc_trim[7:0] type r/w reset 11111111 bit name function 7:0 lposc_ trim[7:0] low power (24 mhz) oscillator trimming. 16% range with 0.14 % resolution. setting all the bits to low will maximize the fre- quency of operation.
SI4010-C2 48 rev. 1.0 sfr address = 0xbe sfr definition 15.2. sysgen bit76543210 name sysgen_ shut- down re-served pwr_1st _time rtc_ tickclr port_ hold sysgen_div[2:0] type r/w r r w r/w r/w reset 00?00000 bit name function 7 sysgen_ shut- down system general shutdown. setting this bit causes shutdown of mcu an d most analog. recovery from this is via ? falling edge on any gpio, which results in a power up and a power on reset. this is the bit that shuts down the power to nearly everything. 0: normal operation 1: shutdown. do not use this bit directly. it is recommended to use the vsys_shutdown() api call. 6 reserved read as 0. write has no effect. 5 pwr_1st_ time initial powerup indicator. read only register. it will get set when powe r up was caused by a battery insertion. 4 rtc_ tickclr real time clock clear. 0: normal operation 1: clears the real time clock 5.12us counter. 3 port_ hold port hold. this bit needs to be set before shutting do wn, it delays any button pushes that occur between this bit setting and shutdown until the chip completes shutdown, to ensure the shutdown process cannot be interrupted. 0: normal operation 1: holds gpio port values until shutdown is complete 2:0 sysgen_ div[2:0] system clock generator divider. system clock divider control to generate the system clock. 000: 24 mhz; div = 1 001: 12 mhz; div = 2 010: 6.0 mhz; div = 4 011: 3.0 mhz; div = 8 100: 1.5 mhz; div = 16 101: 0.75 mhz; div = 32 110: 0.375 mhz; div = 64 111: 0.1875 mhz; div = 128
rev. 1.0 49 SI4010-C2 16. crystal oscillator (xo) the crystal oscillator produces an accurate clock reference for app lications demanding a high-accuracy transmit carrier frequency. it uses a 1-pin crystal oscillator circuit (colpitt 's oscillator) and the output is con- nected to the frequency counter. when crystal is used , the accuracy of the radio center frequency is deter- mined by the parameters of the crystal (such as load capacitance, crystal accuracy, etc.) and the parasitic of the pcb associated with the crystal circuit. to reduce the impact of these crystal parameters and to guarantee safe startup of the oscillato r, the user has to do the following: ? check the crystal data sheet for the ?cload? capacitor value that should be placed across the crystal?s terminals to o scillate at the correct frequency ? if cload > 14 pf, xo_lowcap bit of the bxo_ctrl register have to be set to 0. in this case, the input capacitance of the xtal pin of the si4010 is approximately 5.5 pf, so a (cload ? 5.5)pf capacitor should be placed externally across the crystal terminals. ? if cload < 14 pf xo_lowcap bit of the bxo_ctrl register hav e to be set to 1. in this case, the input capacitance of the xtal pin of the si4010 is approximately 3 pf, so the external capacitor placed across the crystal has to be (cload ? 3)pf. 16.1. register description xreg address = 0x4016 xreg definition 16.1. bxo_ctrl bit765432 1 0 name reserved reserved reserved reserved reserved reserved xo_lowcap xo_ena type r/w r/w reset 000000 0 0 bit name function 7:2 reserved reserved. 1 xo_ lowcap xo low capacitance. bit should be set for crystals that requir e less than 14 pf of total capacitance. 0: crystal requires 14 pf or more of total capacitance. 1: crystal requires less than 14 pf of total capacitance. 0xo_ena enable xo. note that operation of the xo requires that the bandgap be enabled with the system module function api. the input xo_ckgoo d status bit is in the sfr system reg- ister. 0: crystal oscillator disabled. 1: crystal osc illator enabled.
SI4010-C2 50 rev. 1.0 17. frequency counter the frequency counter allows the measurement of the ra tio of two selected clock sources: a low frequency clock which defines a counting interval, and a high frequency clock which is counted. the frequency counter consists of an interval counter, driven by one of the six clock sources. programming of the interval counter determines how long the main coun ter will count one of the two high speed clocks, lc oscillator or divider output. figure 17.1. frequency counter block diagram the block diagram of the frequency counter is in fi gure 17.1. when the fc_mode=0, the frequency coun- ter is disabled. the only way to disable the frequ ency counter is to set the fc_mode=0. the frequency counter stops counting immediately, so it can be restarted by setting fc_mode to some functional mode immediately. if the frequency counter is enabled by setting fc_mode to other than the 0 value, it enters the idle state. to start the counter, the interval counter has to be tr iggered by writing 1 to t he fc_busy bit. by writing fc_busy=1, the fc_done bit gets cleared as well. t he user can also clear the fc_done bit in software after reading the main fc_count value. once the interval counter is triggered, and after several clk_sys cycles synchronization delay it waits for the first rising edge of the clk_int clock, which is the output of the in terval counter clock selector mux. it then enables the main frequency counter fc_count clock. after the interval counter counts the interval specified by fc_interval sfr regi ster, another rising edge of the clk_int stops the clocks to the main fc_count counter. the interval counter edge to edg e counting and main fc_count clock enable is measured very accurately in between the clk_int rising edges. interval counter fc_count (lword lfccount) fc_ctrl fc_done fc_busy fc_div_sel interrupt fc_mode fc_interval 0 1 0 1 2 3 4 5 5 7 fc_ctrl fc_done fc_busy fc_div_sel fc_mode 3 new count trigger long word 4 byte result count read from xreg lc_osc/2 divider clk_ref port controller gpio[3] clk_osc (24mhz) clk_sys xtal oscillator clk_xo gpio[0] reserved sleep timer freq counter disabled clk_int reserved
rev. 1.0 51 SI4010-C2 when the interval counter is finished with the interval count, it clears the fc_busy=0 bit and after a few cycles of clk_sys synchronization delay it sets the fc_done=1 bit. both interval counter and main fc_count counter are stopped and the main fc_c ount keeps the accumulated value until the fre- quency counter is disabled or triggered again. the 23 bit fc_count value can be read as a 4 byte long word, lfccount , from the xreg register in xdata. when the counter is counting and fc_busy=1, then reading the fc_count value returns the on the fly changing value of the fc_count counter. the frequency counter is restartable. if 1 is writte n to fc_busy while the frequency counter is busy then the current fc_count result is discarded, main fc_c ount is reset, and the in terval counter is trig- gered, waiting for the fi rst rising edge of the clk_int clock. the count interval is chosen with the fc_interval sfr register. the number of interval count cycles (count cycles of the low frequency clock) = (2+fc_interval[0])*( 2^fc_interval[5:1]). note: fc_interval is not allowed to take on numbers hi gher than 43. if the number is higher than 43, then the calculated number or interval count cycles is forced to 1. even though 43 is the maximum fc_interval setting, lower fc_interval settings can cause the 23-bit frequency counter to overflow depending on the ratio between the frequency counter clock and the interval clock. generally, the ratio between these clocks should be carefully selected to prevent overflow of the fr equency counter (unless overflow is explicitly desired). ? the output of the frequency counter is in the xreg fc_count. the main function of the frequency counter is to ai d the frequency casting operation, however it can be used for measuring purposes, using the calibrated lc oscillator as a ti me base. one example is enhancing the accuracy of the internal timers of the mcu. see ?an526: si4010 api additional library description? for more details. the user is recommended to use the frequency coun ter module function api to set the sfrs associated to the frequency counter.
SI4010-C2 52 rev. 1.0 17.1. register description sfr address = 0x9b sfr definition 17.1. fc_ctrl bit76543210 name fc_done fc_busy fc_div_ sel reserved fc_mode[2:0] type r/w r/w r/w r r/w reset 000 0 0 bit name function 7 fc_done frequency counter done. counting done, interrupt generation level si gnal. must be cleared by software isr. it is also cleared if 1 is written to fc_busy, which denotes the start of the next count. any value can be written here, so one can invoke interrupt just writing 1 here. 0: frequency counter is counting 1: frequency counter done counting, must be cleared by software isr 6fc_busy frequency counter busy. frequency counter is busy co unting. falling edge of the fc_busy signal sets the fc_done=1. writing 1 to this bit triggers a new fc counting cycle. fc is restartable, so any wr 1 to this bit rest arts the fc and discards what the fc was currently doing. 0: frequency counter is not bu sy, falling edge sets fc_done=1 1: writing 1 restarts the frequency counter 5 fc_div_ sel frequency counter divider select. selection control of source of clock. it chooses between lc and divider. if the fre- quency counter is not enabled, fc_mode= 0, then both signals mentioned above are in their inactive states. 0: lcosc 1: divider 4:3 reserved read as 0x0. write has no effect. 2:0 fc_mode [2:0] frequency counter mode control register. 000: frequency counter disabled 001: interval: clk_ref .. reference clock from gpio 010: interval: clk_osc .. undivided output of low power osc (24 mhz) 011: interval: clk_sys .. system clo ck, divided output of low power osc 100: interval: clk_xo .. xo oscillator 101: reserved 110: interval: sleep timer output 111: reserved
rev. 1.0 53 SI4010-C2 sfr address = 0x9d xreg address = 0x4008 sfr definition 17.2. fc_interval bit76543210 name reserved reserved fc_interval[5:0] type r/w reset 00 bit name function 7:6 reserved reserved. 5:0 fc_ interval [5:0] frequency counter interval. controls number of interval clock cycles in an interval. n_cycles = (2+fcnt_interval [0])*(2^fcnt_interval[5:1]) note that fcnt_interval is allowed to take on values no higher than 43. if the number higher than 43 is used then the the interval counted is forced to n_cycles = 1. xreg definition 17.3. ifc_count bit3210 name ifc_count[3:0] type r reset 0x00 0x00 0x00 0x00 bit name function 3:0 ifc_count[0:3] frequency counter output. counter output value. accessed as 4 bytes (long word) in big endian fashion. upper bits [31:23] are read as 0. when the counter is running and the value is read then the current on the fly value will be read.
SI4010-C2 54 rev. 1.0 18. sleep timer the si4010 includes a very low-power sleep timer that can be used to support the transmit duty cycle requirements of the etsi specificat ion or self-wakeup for button independe nt applications. it consist of a low speed (~2.1 khz), very low power oscillator with a 24 bit down counter. when programmed to its maxi- mum interval it takes ~2.1 hours to count down to zero. when it co unts down to zero, it automatically pow- ers down completely. the sleep timer can also be programmed to wake up the chip if the chip was powered down. control of the sleep timer is don e with the api sleep timer module functions. 19. bandgap and ldo power management is provided on chip with ldo regulato rs for the internal analog and digital supplies, va and vd, respectively. the power-on reset circuit monitors the power applied to the chip and generates a reset signal to set the chip into a known state. the bandgap produces voltage and current references for the analog blocks in the chip and can be shut down when the analog blocks are not used. control of the bandgap and ldo is done with the system module function api vsys_bandgapldo. 20. low leakage hvram the low-leakage hvram provides 8 by tes of ram memory which keeps its contents in all states including standby mode as long as the supply voltage is applied to the chip. control of the hvram is done with the api hvram module functions. 21. temperature sensor the on-chip temperature sensor me asures the internal temperature of the chip and the temperature demodulator converts the temperature sensors? output into a binary number representing temperature and is used to compensate the frequency of the lcosc when the temperature changes. temperature com- pensation of the lcosc is automatically taken care of by the single transmission loop module function api.
rev. 1.0 55 SI4010-C2 22. cip-51 microcontroller the mcu system controller core is the cip-51 microcon troller. the cip-51 is fully compatible with the mcs-51? instruction set; standard 803x/805x assemble rs and compilers can be used to develop soft- ware. the mcu family has a superset of all the peri pherals included with a standard 8051. the cip-51 also includes on-chip debu g hardware, and interfaces directly with the analog and digital subsystems pro- viding a complete rf transmitter solution in a single integrated circuit. the cip-51 microcontroller core implements the standard 8051 organization and peripherals as well as additional custom peripherals and functions to extend its capability. the cip-51 includes the following fea- tures: performance the cip-51 employs a pipelined architecture that grea tly increases its instruction throughput over the stan- dard 8051 architecture. in a standar d 8051, all instructions except for mul and div take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 mhz. by contrast, the cip-51 core executes 70% of its instructions in one or tw o system clock cycles, with no instructions taking more than eight system clock cycles. figure 22.1. cip-51 block diagram l fully compatible with mcs-51 instruction set l 24 mips peak throughput with 24 mhz clock l 0 to 24 mhz clock frequency l extended interrupt handler l power management modes l on-chip debug logic l program and data memory security data bus tmp1 tmp2 prgm. address reg. pc incrementer alu psw data bus data bus memory interface mem_address d8 pipeline buffer data pointer interrupt interface system_irqs emulation_irq mem_control control logic a16 program counter (pc) stop clock reset idle power control register data bus sfr bus interface sfr_address sfr_control sfr_write_data sfr_read_data d8 d8 b register d8 d8 accumulator d8 d8 d8 d8 d8 d8 d8 d8 mem_write_data mem_read_data d8 sram address register sram d8 stack pointer d8
SI4010-C2 56 rev. 1.0 with the cip-51's maximum system clock at 24 mhz, it has a peak throughput of 24 mips. the cip-51 has a total of 109 instructions. the table below shows the to tal number of instructions in the function of the required clock cycles. 22.1. instruction set the instruction set of the cip-51 system controller is fully compatible with the standard mcs-51? instruc- tion set. standard 8051 development tools can be used to develop software for the cip-51. all cip-51 instructions are the binary and fu nctional equivalent of their mcs-51? counterparts, including opcodes, addressing modes and effect on psw flags. however, in struction timing is different than that of the stan- dard 8051. 22.1.1. instruction and cpu timing in many 8051 implementations, a distinction is ma de between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. however, the cip-51 implementation is based solely on clock cycle timing. all instruction ti mings are specified in terms of clock cycles. due to the pipelined architecture of the cip-51, most instructions execute in the same number of clock cycles as there are program bytes in the instruction. conditional branch instruct ions take one less clock cycle to complete when the branch is not taken as oppo sed to when the branch is taken. table 22.1 is the cip-51 instruction set summary, which includes the mnemonic, number of bytes, and number of clock cycles for each instruction. clocks to execute 1 22/333/444/55 8 number of instructions 26 50 5 14 7 3 1 2 1
rev. 1.0 57 SI4010-C2 table 22.1. cip-51 instruction set summary mnemonic description bytes clock cycles arithmetic operations add a, rn add register to a 1 1 add a, direct add direct byte to a 2 2 add a, @ri add indirect ram to a 1 2 add a, #data add immediate to a 2 2 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 2 addc a, @ri add indirect ram to a with carry 1 2 addc a, #data add immediate to a with carry 2 2 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 2 subb a, @ri subtract indirect ram from a with borrow 1 2 subb a, #data subtract imme diate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 2 inc @ri increment indirect ram 1 2 dec a decrement a 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 2 dec @ri decrement indirect ram 1 2 inc dptr increment data pointer 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 8 da a decimal adjust a 1 1 logical operations anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 2 anl a, @ri and indirect ram to a 1 2 anl a, #data and immediate to a 2 2 anl direct, a and a to direct byte 2 2 anl direct, #data and immediate to direct byte 3 3 orl a, rn or register to a 1 1 orl a, direct or direct byte to a 2 2 orl a, @ri or indirect ram to a 1 2 orl a, #data or immediate to a 2 2 orl direct, a or a to direct byte 2 2 orl direct, #data or immediate to direct byte 3 3 xrl a, rn exclusive-or register to a 1 1 xrl a, direct exclusive-or direct byte to a 2 2 xrl a, @ri exclusive-or indirect ram to a 1 2 xrl a, #data exclusive-or immediate to a 2 2 xrl direct, a exclusive-or a to direct byte 2 2
SI4010-C2 58 rev. 1.0 xrl direct, #data exclusive-or immediate to direct byte 3 3 clr a clear a 1 1 cpl a complement a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 swap a swap nibbles of a 1 1 data transfer mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 2 mov a, @ri move indirect ram to a 1 2 mov a, #data move immediate to a 2 2 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate to register 2 2 mov direct, a move a to direct byte 2 2 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 3 mov direct, @ri move indirect ram to direct byte 2 2 mov direct, #data move immediate to direct byte 3 3 mov @ri, a move a to indirect ram 1 2 mov @ri, direct move direct byte to indirect ram 2 2 mov @ri, #data move immediate to indirect ram 2 2 mov dptr, #data16 load dptr with 16-bit constant 3 3 movc a, @a+dptr move code byte relative dptr to a 1 3 movc a, @a+pc move code byte relative pc to a 1 3 movx a, @ri move external data (8-bit address) to a 1 3 movx @ri, a move a to external data (8-bit address) 1 3 movx a, @dptr move external data (16-bit address) to a 1 3 movx @dptr, a move a to external data (16-bit address) 1 3 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a, rn exchange register with a 1 1 xch a, direct exchange direct byte with a 2 2 xch a, @ri exchange indirect ram with a 1 2 xchd a, @ri exchange low nibble of indirect ram with a 1 2 boolean manipulation clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 table 22.1. cip-51 instruction set summary (continued) mnemonic description bytes clock cycles
rev. 1.0 59 SI4010-C2 anl c, bit and direct bit to carry 2 2 anl c, /bit and complement of direct bit to carry 2 2 orl c, bit or direct bit to carry 2 2 orl c, /bit or complement of direct bit to carry 2 2 mov c, bit move direct bit to carry 2 2 mov bit, c move carry to direct bit 2 2 jc rel jump if carry is set 2 2/3 jnc rel jump if carry is not set 2 2/3 jb bit, rel jump if direct bit is set 3 3/4 jnb bit, rel jump if direct bit is not set 3 3/4 jbc bit, rel jump if direct bit is set and clear bit 3 3/4 program branching acall addr11 absolute subroutine call 2 3 lcall addr16 long subroutine call 3 4 ret return from subroutine 1 5 reti return from interrupt 1 5 ajmp addr11 absolute jump 2 3 ljmp addr16 long jump 3 4 sjmp rel short jump (relative address) 2 3 jmp @a+dptr jump indirect relative to dptr 1 3 jz rel jump if a equals zero 2 2/3 jnz rel jump if a does not equal zero 2 2/3 cjne a, direct, rel compare direct byte to a and jump if not equal 3 4/5 cjne a, #data, rel compare immediate to a and jump if not equal 3 3/4 cjne rn, #data, rel compare immediate to register and jump if not equal 33/4 cjne @ri, #data, rel compare immediate to indirect and jump if not equal 34/5 djnz rn, rel decrement regist er and jump if not zero 2 2/3 djnz direct, rel decrement direct byte and jump if not zero 3 3/4 nop no operation 1 1 table 22.1. cip-51 instruction set summary (continued) mnemonic description bytes clock cycles
SI4010-C2 60 rev. 1.0 notes on registers, operands and addressing modes: rn ?register r0?r7 of the currently selected register bank. @ri ?data ram location addressed indirectly through r0 or r1. rel ?8-bit, signed (twos complement) offset relative to th e first byte of the followi ng instruction. used by sjmp and all conditional jumps. direct ?8-bit internal data location?s address. this could be a direct-access data ram location (0x00? 0x7f) or an sfr (0x80?0xff). #data ?8-bit constant #data16 ?16-bit constant bit ?direct-accessed bit in data ram or sfr addr11 ?11-bit destination address used by acall a nd ajmp. the destination must be within the same 2 kb page of program memory as the first byte of the following instruction. addr16 ?16-bit destination address used by lcall and ljmp. the destination may be anywhere within the 8 kb program memory space. there is one unused opcode (0xa5) that performs the same function as nop. all mnemonics copyrighted ? intel corporation 1980.
rev. 1.0 61 SI4010-C2 22.2. cip-51 re gister descriptions following are descriptions of sfrs related to the operati on of the cip-51 system controller. reserved bits should always be written to the value indicated in the sfr description. future product versions may use these bits to implemen t new features in which case the reset value of the bit will be the indicated value, selecting the feature's default state. detailed descriptions of the remaining sfrs are included in the sec- tions of the data sheet associated wit h their corresponding system function. sfr address = 0x82 sfr address = 0x83 sfr definition 22.1. dpl bit76543210 name dpl[7:0] type r/w reset 00000000 bit name function 7:0 dpl[7:0] data pointer low. the dpl register is the low byte of the 16-bit dptr. sfr definition 22.2. dph bit76543210 name dph[7:0] type r/w reset 00000000 bit name function 7:0 dph[7:0] data pointer high. the dph register is the high byte of the 16-bit dptr.
SI4010-C2 62 rev. 1.0 sfr address = 0x81 sfr address = 0xe0; bit-addressable sfr definition 22.3. sp bit76543210 name sp[7:0] type r/w reset 00000111 bit name function 7:0 sp[7:0] stack pointer. the stack pointer holds the location of the to p of the stack. the stack pointer is incre- mented before every push operation. the sp register defaults to 0x07 after reset. sfr definition 22.4. acc bit76543210 name acc[7:0] type r/w reset 00000000 bit name function 7:0 acc[7:0] accumulator. this register is the accumulator for arithmetic operations.
rev. 1.0 63 SI4010-C2 sfr address = 0xf0; bit-addressable sfr definition 22.5. b bit76543210 name b[7:0] type r/w reset 00000000 bit name function 7:0 b[7:0] b register. this register serves as a second accumu lator for certain arithmetic operations.
SI4010-C2 64 rev. 1.0 sfr address = 0xd0; bit-addressable sfr definition 22.6. psw bit76543210 name cy ac f0 rs[1:0] ov f1 parity type r/w r/w r/w r/w r/w r/w r reset 00000000 bit name function 7cy carry flag. this bit is set when the last arithmetic oper ation resulted in a carry (addition) or a bor- row (subtraction). it is cleared to logi c 0 by all other arithmetic operations. 6ac auxiliary carry flag. this bit is set when the last arithmetic operat ion resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. it is cleared to logic 0 by all other arith- metic operations. 5f0 user flag 0. this is a bit-addressable, general purp ose flag for use under software control. 4:3 rs[1:0] register bank select. these bits select which register bank is used during register accesses. 00: bank 0, addresses 0x00-0x07 01: bank 1, addresses 0x08-0x0f 10: bank 2, addresses 0x10-0x17 11: bank 3, addresses 0x18-0x1f 2ov overflow flag. this bit is set to 1 under the following circumstances: l an add, addc, or subb instructi on causes a sign-change overflow. l a mul instruction results in an overflow (result is greater than 255). l a div instruction causes a divide-by-zero condition. the ov bit is cleared to 0 by the add, a ddc, subb, mul, and div instructions in all other cases. 1f1 user flag 1. this is a bit-addressable, general purp ose flag for use under software control. 0parity parity flag. this bit is set to logic 1 if the sum of the ei ght bits in the accumulator is odd and cleared if the sum is even.
rev. 1.0 65 SI4010-C2 23. memory organization the memory organization of the si4010 is similar to that of a standard 8051. there are two separate mem- ory spaces: program memory and data memory. program and data memory share the same address space but are accessed via different instruction types. however, this device is unique since it has the pro- gram and data memory spaces combined into one. this is called a unified code and xdata memory. the device has a standard 8051 program and data address configuration. it includes 256 bytes of internal data ram, with the upper 128 bytes dual-mapped. in direct addressing accesses the upper 128 bytes of general purpose ram, and direct addressing accesse s the 128 byte sfr address space. the lower 128 bytes of internal ram are accessible via direct and indirect addressing. the first 32 bytes are addressable as four banks of general purpose registers, and the next 16 bytes can be byte addressable or bit address- able. apart from the cpu core related internal memory, the device has the following memories: ? 4.5 kb of ram .. it can be used both as prog ram code and external data xdata memory ? 12 kb of rom .. it holds the s ilicon labs provided api (application programming interface) routines. the rom is not readable by the user. ? 256b hardware control registers mapped to xdata address space (xreg) ? 8 kb of one time programmable (otp) non-volatile memory (nvm) ? 128 bits of multiple time programmable (mtp) eeprom. the eeprom has an endurance of 50,000 updates per bit. see figure 23.1 for t he mcu system memory map: figure 23.1. address space map after the boot 0x0000 ram 4.5k 0xffff 0x0000 0xffff direct & inidirect addressing upper 128 ram indirect addressing only sfr (data) direct addressing only 0x00 0x20 0x80 0xff 0x80 0xff code/ xdata xdata 0x8000 0x8000 0x4000 0xc000 0x4000 64kb 16kb mcu view of unified ram address space nvm (otp) 8k mtp (eeprom) 128 bits rom 12k xreg registers 0x1f bit addressable 0x2f 0x30 0x7f data/idata lower 128 ram bytes, direct and indirect addressing 0x11ff 0xafff 0x40ff
SI4010-C2 66 rev. 1.0 23.1. program memory program memory consists of 4.5 kb for ram and 12 kb of rom. the device employs a unified code/xdata ram memory. on 8051 architecture the ex ternal data memory (xdata) space is physically different from the program memory (code); they can be accessed with different instructions. on this device the ram can store both code and xdata at any location. the program memory is commonly called code memory, residing in code address space. both movc and movx instructions can be used to read data from the code/xdata address space. the rom holds the silicon labs proprietary code a nd cannot be read by a us er. only code can be exe- cuted from rom. if read is attemp ted by movc or movx instructions from rom area the read value is undetermined. the nvm and mtp memories are not mapped to the cpu address space. 23.2. internal data memory the device implements 256 bytes of internal ram mapped into the data memory space from 0x00 through 0xff. the lower 128 bytes of data memory are used for general purpose registers and memory. either direct or indirect addressing may be used to acce ss the lower 128 bytes of data memory. locations 0x00 through 0x1f are addressable as four banks of gene ral purpose registers, each bank consisting of eight byte-wide registers. the next 16 bytes, locations 0x20 through 0x2f, may either be addressed as bytes or as 128 bit locations accessible with the direct addressing mode. the upper 128 bytes of data memory are accessible only by indirect addressing. this region occupies the same address space as the special function registers ( sfr ) but is physically separate from the sfr space. the addressing mode used by an instructio n when accessing locations above 0x7f determines whether the cpu accesses the upper 128 bytes of data memory space or the sfrs. instructions that use direct addressing will access the sfr space. instructions using indirect addressing above 0x7f access the upper 128 bytes of data me mory. figure 23.1 illustrates the data memory organization. 23.3. external data memory even though it is called external memory, it resides on the chip. this is the data memory, up to 64 kb in size, which is accessible by movx instructions. for the or iginal mcs-51? archit ecture this memory resided physically external to the chip. this memory is commonly referred as xdata memory. the device implements shared code/xdata memory. the 4.5 kb of ram is shared between the code and xdata. the cpu can run code from any location of that ram, can read any location using movc and movx instructions, and can write any location by using movx instruction. important note: linker of the user application has to be given proper regions of code and xdata mem- ory, which are mutually exclusive. therefore, for ex ample, the user cannot se t the code region to be 0x0000 .. 0x1000 and xdata region to be the very same at the same time. one has to specify two non- overlapping regions in the ram area instead. 23.4. general purpose registers the lower 32 bytes of data memory, locations 0x00 through 0x1f, may be addressed as four banks of gen- eral-purpose registers. each bank consists of eigh t byte-wide registers designated r0 through r7. only one of these banks may be enabled at a time. two bi ts in the program status word, rs0 (psw.3) and rs1 (psw.4), select the active register bank. this allows fast context switching when entering subroutines and interrupt service routines. indire ct addressing modes use register s r0 and r1 as index registers.
rev. 1.0 67 SI4010-C2 23.5. bit addressable locations in addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2f are also accessible as 128 individually addressable bits. each bit has a bit address from 0x00 to 0x7f. bit 0 of the byte at 0x20 has bit address 0x00 while bit 7 of the byte at 0x20 has bit address 0x07. bit 7 of the byte at 0x2f has bit address 0x7f. a bit access is distinguished from a full byte access by the type of instruction used (bit source or destinat ion operands as opposed to a byte source or destina- tion). the mcs-51? assembly language allows an alternate notation for bit addressing of the form xx.b where xx is the byte address and b is the bit position within the byte. for example, the instruction: mov c, 22.3h moves the boolean value at 0x13 (bit 3 of the byte at location 0x22) into the carry flag. 23.6. stack a programmer's stack can be located anywhere in the 256 byte data memory. the stack area is designated using the stack pointer (sp, addres s 0x81) sfr. the sp will point to the last location used. the next value pushed on the stack is placed at sp +1 and then sp is incremented. a re set initializes the stack pointer to location 0x07; therefore, the first value pushed on th e stack is placed at location 0x08, which is also the first register (r0) of register bank 1. thus, if more than one register bank is to be used, the sp should be initialized to a location in the data memory not being used for data storage. the stack depth can extend up to 256 bytes. 23.7. special functi on registers (sfr) the direct-access data memory locations from 0x80 to 0xff constitute the sp ecial function registers (sfrs). the sfrs provide control and data exchang e with the cip-51's resources and peripherals. the cip-51 duplicates the sfrs found in a typical 805 1 implementation as well as implementing additional sfrs used to configure and access the sub-systems uni que to the mcu. this allows the addition of new functionality while retaining compat ibility with the mcs-51? instruction set. table 25.1 lists the sfrs implemented in the device. the sfr registers are accessed whenever the direct addressing mode is used to access memory loca- tions from 0x80 to 0xff. sfrs with addresses ending in 0x0 or 0x8 (e.g. p0, p1, ie, etc.) are bit-address- able as well as byte-addressable. all other sfrs are byte-addressable only. unoccupied addresses in the sfr space are reserved for future use. accessing these areas will have an indetermi nate effect and should be avoided. refer to the corresponding pages of the data sheet for a detailed description of each register. 23.8. registers mapped to xdata address space (xreg) given the extensive requirement for the numerous hardwa re registers some of the registers are mapped to the xdata space as shown in figure 23.1. those registers are accessible only by movx instructions and are viewed from the cpu as a regular external xdata memory. registers which are more than single byte wide are organized in big endian fashion (most signific ant byte on the lowest address) to comply with the keil development toolchain. they can be declared as regular variables in higher level languages, like c. map of user accessible xreg registers is in table 25.3. 23.9. nvm (otp) memory nvm memory is only accessible indi rectly through silicon labs provided api functions for nvm access ini- tialization and read of formatted blocks of data g enerated by the nvm program mer. programming of the nvm can be only done by silicon lab s provided tools. it is not possible to program the nvm by writing to registers. see ?system boot and nvm programming? on page 69 for details.
SI4010-C2 68 rev. 1.0 the maximum number of read operations of the nvm memory is limited, but this limitation has effect only in extreme conditions. consult the el ectrical specification section in this document, and with ?anxxx nvm reliability analysis.? 23.10. mtp (eeprom) memory the mtp memory is a special block not organized as a usual memory. the memory output is mapped to the xdata address space as a xreg register (abmtp_rdata[16]) 16 byte read only array at addresses 0x4040 .. 0x404f. writing to the mt p memory can be done only indire ctly by using the silicon labs pro- vided api rom functions. to write to mtp the user must prepare an array of all 16 bytes in code/xdata ram. there is no byte access to mtp. even if only a single bit is to be chan ged in mtp, the current cont ent must be copied to the code/xdata ram in full, all 16 bytes. then the desi red bit has to be changed in that ram copy and an api function has to be called to program the 16 byte changed data from ram to mtp. the user can use the api mtp copy call to get the cu rrent content of mtp into code/xdata ram for modifications. if the mtp bit is not changing value the programming cycl e is not counted against the maximum bit change dura- bility of mtp. therefore, programming the 16 byte mtp content unc hanged from the curr ent value has no effect on the longevity of the mtp. there is no direct write access to mtp through registers. silicon labs api rom function s must be used. xreg address = 0x4040 xreg definition 23.1. abmtp_rdata[16] byte 15 14 ... 1 0 name abmtp_rdata[0:15] type r reset ? ?... ?? byte name function 15:0 abmtp_ rdata[0:15] mtp read data. mtp 16-byte read only array.
rev. 1.0 69 SI4010-C2 24. system boot and nvm programming the device does not include a flash memory for permanent code or data storage. instead, the device con- tains 4. 5kb of ram, which can serve as a unifie d code and xdata ram memory. the device contains 8 kb of nvm (otp) memory for user code and data st orage. small part of the nvm is reserved for silicon labs factory use and is not available to a user. in general more than 7 kb of nvm will be available for user application use. 24.1. startup overview the code cannot be run directly from nvm, since it is not mapped directly to the cpu address space. instead, upon device reset, the device goes through a boot process during which the factory chip configu- ration and the user application code and data is copi ed from nvm to the code/xdata ram. only after the boot process finishes the user code starts be ing executed from code/xdata ram address 0x0000. therefore upon reset the device does not execute the user code immediately, but only after the boot pro- cess finishes. the time in between the device wakeup , either caused by cycling the power or waking up from the shutdown mode by button press, de pends on the size of the user code load. in general the startup time is about 2ms of fixed time plus 3.6 ms per 1 kb of user application code. for example, 4 kb application will incur tstartup = 2 ms + 3.6 ms x user _kb = 2 ms + 3.6 ms x 4 = 16.4 ms startup time before the user application starts being executed. for debugging purpos es user will not program the nvm, but will use the ram for code development. in that case the device will only contai n factory settings and go through mu ch shorter startu p routine, which would take less than 2 ms to finish.
SI4010-C2 70 rev. 1.0 24.2. reset reset circuitry allows the controller to be easily placed in a pred efined default condition. see ?reset sources? on page 106 for details. 24.3. chip program levels the boot process starts by reading the nvm configuration bytes in the factory region of nvm. the infor- mation about the programmed level of the chip is re ad first and the boot process acts accordingly. after boot, the program level of the chip can be read as nvm_blown [2:0] field in the prot0_ctrl ? register. from user point of view there are 3 program levels of the chip: 1. factory .. blank part leaving the factory. the factory ch ip calibration is writ ten into nvm. rom and nvm factory region is not readable by the user. part can be used with debugging chain for software development and user load can be programmed to the part. boot process initializes the part based on the factory settings. 2. user .. same as factory (blank) part, but with the user region in the nvm programmed with user code. the boot process will initialize the part according to the factory settings and then (see note 1. in section ?24.5. device b oot process?) copies the user load to the code/xdata or iram based on the user load. the code is not automatically run (see note 2. in section ?24.5. device boot process?). the part can be used with ide for furt her software developmen t. the part is still opened for further nvm programming and the user can add additional data to the user region in the nvm. debugging of the code loaded from nvm is possible. the user can modify the boot behavior of the user part by controlling two bits described later in the boot sequence description. ? this program level can be used two ways: ? user programs the user code to check the load before finalizing the product. ? silicon labs program most of the user code into the chip. then the customer will add additional information specific fo r each chip on his own. for example, the customer may c hose to let silicon labs program all the application data, but wants to program security keys into each chip on their own. this user level would be the chip program level delivered to a customer. 3. run .. mission mode part, fully programmed for use in the field. no further nvm programming possible, no c2 interface access enabled, wit h the exception of special mode for retest. no po ssibility of ide debug. the boot process is the same as in the case of user part, but after the user load is copied from nvm to ram, the boot loader executes a jump to ram address 0x0000 and the user application is executed. the c2 is not enabled in this mode with the retest exception, briefly described in this document. the ide debugging environment can be used only with the factory and user program chip levels, not with the run part.
rev. 1.0 71 SI4010-C2 24.4. nvm organization the 8 kb nvm (otp) memory is virtually mapped to the device address space 0xe000 .. 0xffff. how- ever, cpu can access nvm only indirectly using the predefined api calls in rom. the nvm address region is organized in the following fashion: 1. factory region .. factory settings cr itical for chip functions. size is variable based on the device configuration. 2. user region .. region available for user application load at boot time. if the user application is not going to use overlays, then this will be the only user data region used. 3. user app optional region .. optional region not visible at boot time. if the us er application is using overlays, then the overlay code will be stored in th is region. it will be up to the user to load the application code from the nvm to code/xdata ra m at runtime based on the user application request. application note will be devoted to this technique. 4. reserved region .. last 64 bytes of nvm are reserved for factory use and not available for user load. the user load can occupy the rest of the nvm. the user may decide that he will us e overlays. that means that the boot routine will not copy a ll the data from nvm to ram upon boo t, but during t he runtime of the user program the program itself will load data from nvm to th e ram as desired. only the user region is known to boot routine a nd will be loaded during boot. the user app region is the data region available to the user for a load to be loaded at runtime by the user program. the user will have to call the api nvm copy routine in that case. ?a n518: si4010 memory over- lay technique" describes this proce ss in detail. in such a scenario, th is nvm region will not be loaded by boot, but by the user application. that region of nvm is labeled as user app region in figure 24.1, ?nvm address map?. boot routine will not know about th e data there.
SI4010-C2 72 rev. 1.0 figure 24.1. nvm address map 24.5. device boot process the boot process works in the following sequence: 1. boot is invoked by cycling power to the internals of the chip (which includes power cycle to the whole chip), waking up by button press, by the sleep timer, or by pressing a reset button in the ide development platform. 2. the device will read the factory part of the nvm to determine the device configuration and load the configuration values to appropriate registers and co de/xdata memory locations. part of this process is setting the boot variable block at the end of the code/xdata memory. 3. if the program level is factory then the boot process will stop and will not execute any code. it will wait in an infinite loop for the debugging chain to load a user application to code/xdata ram and to allow that code execution from the ide. more specific ally, the boot hardware wa its for the code_run_por or code_run_sys bits to be set in the boot_f lags register. when usin g debugging chain and ide, this is taken care of automatically by the ide and there is no user intervention required. 4. if the program level is user then the same procedure is followed as for the factory device. after that the boot procedure automatically (see note 1.) continues to load user region from nvm to code/xdata ram and iram. after it finishes the devi ce does not execute any code (see note 2.) and goes to the same waiting infinite loop as described in item 3. for factory device. ? the user can modify the boot behavior of the user part by controlling the following two bits: note 1. boot_trim_por bit in boot_flags .. register cleared on power on reset. if this bit is 1, the boot loader will not load the user load but enables c2 and goes to the boot_flags waiting loop. the part will behave as a factory part. this bit has higher priority than the one below. convenient for debugging until the power is cycled. note 2. user_cont bit in prot3_ctrl in nvm .. bit in th e nvm protection register. once set it nvm 8kb 0xe000 factory setup user (boot) user app (app use) optional reserved 64 bytes 0xffff 0xffc0 wboot_nvmuserbeg set by the factory setup optional gap first unread nvm byte address .. user/run part wboot_nvmcopyaddr
rev. 1.0 73 SI4010-C2 cannot be cleared. when this bit is 1, then af ter the factory and user loads are loaded from nvm the boot loader enables c2 and runs the user code immediately, without any wait, by executing long jump to ram ad dress 0x0000. the ide can still ha lt the chip and connect to it in a usual fashion. from the debug point of view there is no change. this bit corresponds to the exe user boot checkout on the nvm programmer gui application. 5. if the program level is run then the same boot procedures is followed as for the user device. when loading the user region is done, the user code is run by jumping to the 0x0000 address in code/xdata ram. the c2 interface is disabled and the chip can no l onger be used with debug chain and ide. the run chip can be opened for retest, but the user has an option to limit retest access or lock the chip out completely. see section ?24.11. retest and retest configuration?. note: if the factory or user part is powered up, the part will wait in an infinite loop, consuming power. only the run part executes code in code/xdata ram automatically. the user can also optionally make the user part to execute loaded code automatically as described above. 24.6. error hand ling during boot at the end of the boot process the bboot_bootstat byte variable contains the final status of the whole boot process. bit field meanings are summarized in sf r definition 24.1. the user application code should read that variable and if its value is other then 0x00 or 0x80, then it should decide whether it is safe to run the application at all. the boot su ccess/fail single bit info rmation is also contained in the boot_flags sfr register for easier access. 24.7. code/xdata ram address map the 4.5 kb for internal ram at the address range 0x00 00 .. 0x11ff is the main area for the user program (code) and external data (xdata). it is a unified memory, referred to as code/xdata ram in this docu- ment, so both cpu code (code) can be executed th ere and external data (xdata) can reside there. external data are the data accessible by movx inst ructions. movc instructions can also be used to access data in that region. after the boot of a run part the cpu starts executing code from address 0x0000 in ram. therefore, user code must occupy the beginning of the ram, followed by the xdata. important : linker of the user application has to be gi ven proper regions of code and xdata memory, which are mutually exclusive. therefore, for example, the user cannot set the code region to be 0x0000 .. 0x1000 and xdata region to be the very same at t he same time. one has to specify two non-overlapping regions for code and xdata in the code/xdata ram area instead. the end of the code/xdata ram is reserved for internal silicon labs use. the code/xdata ram address space is divided into three parts: 1. user code/xdata .. user application load. the boot process copies the user code and external initialized data from nvm to this region. 2. factory data values .. variable length . reserved for silicon labs use. the actual beginning of the silicon labs reserved area in ram can be obtained by reading th e boot word (2 byte) variable wboot_dpramtrimbeg . in big endian fashion it contains an ad dress of the first reserved byte of the ram. user can use the range 0x0000 .. ( wboot_dpramtrimbeg ) - 1 for application code and xdata 3. boot status variables .. variables in the region 0x11 f3 .. 0x11ff are boot status variables set at the end of the boot process to inform the user application abo ut the ram size available for user application and about the final status of the boot process. the visual representation of the ram is in figure 24 .2. the detailed explanation of the boot control data variables are in table 24.1 to sfr definition 24.1.
SI4010-C2 74 rev. 1.0 the user code or user development environment need to pay attention to the cont ent of the following vari- ables. all are stored in big endian fashion (msb at the lower address): ? wboot_dpramtrimbeg .. this variable points to the first oc cupied (by factory data) address of ram. therefore, the user development platform needs to read this variable to determine what the available ram area for user code/xdata is. ? bboot_bootstat .. boot status result. user code should chec k this value at its begi nning. if the value is different than 0x00 then the user could decide not to run its application since there was a problem with the boot. critical registers and variables co rresponding to the nvm programming: ? prot0_ctrl .. this register, described in sfr definition 24.4 , contains the value of the current program level of chip. depending on that value, the nv m programming utility w ill decide what can and cannot be programmed into the nvm. ? prot3_ctrl .. internal byte in the factory region of the nvm controlling th e boot process. it contains all the user code protection bits and modi fication of the user part boot process. ? wboot_nvmuserbeg .. address in nvm of the beginning of the user load. for programming the user load into the nvm, the nvm programming utility has to be properly c onfigured by using this value. the value is read automatically by t he nvm programming utility, and also is available through the ide. depending on the size of the factory load the value of this variable ca n vary in between chip revisions. it could also vary from chip to chip, but that is unlikely. ? wboot_nvmcopyaddr .. first unread address of the nvm during boot. this address contains the nvm address the boot routine would read next. the last byte of the last data block read is at the address that is one less than the content of this variable: ( wboot_nvmcopyaddr ) - 1. the nvm programmer will use this information when additional block user data is needed to be programmed. as long as the part is in a program state user additional blocks can be added to the user load.
rev. 1.0 75 SI4010-C2 figure 24.2. code/xdata ram address map boot_aftertrimexe boot_patchexe r es erved boot xdata 0x0000 factory xdata bboot_bootstat wboot_nvmcopyaddr wboot_nvmuserbeg wboot_dpramtrimbeg user code/ xdata 0x11ff 0x11fd 0x11f3 0x11f5 code/xdata ram 4.5kb 0x11f7
SI4010-C2 76 rev. 1.0 24.8. boot status variables end of the code/xdata ram are reserved for boot status variables. the user must pay attenti on to the content of the wboot_dpramtrimbeg variable. its content points to the first reserved address for factory silicon labs use. important: the code/xdata area from this address on (increasing address) is reserved and must not be overwritten by user nvm load at boot time nor by user application at runtime. if this area is accidentally overwritten by user app lication the chip will behave un predictably. there is no hardware protection for this region. note that depending on the revision of the chip the factory xdata area can vary in size. the area is refreshed when reset is issued. boot status byte can or should be read by the user application at the very beginning to determine whether the copying of the factory and user data from nvm to desired ram de stination was successful or not. when there are no errors, the value the bboot_bootstat variable should be 0x00 or 0x80. any other value denotes a boot error. the user application then can deci de whether to run or stall, if the user application was actually loaded to ram. if the boot fails and the user application is not loaded to ram, then unpredictable results may occur. the bit 7 of this vari able contains a read value of gpio[0] at the very beginning of the boot before the xo was optionally turned on. table 24.1. boot xdata status variables register addr type description wboot_dpramtrimbeg 0x11f3 word* address of the first occupied byte by the silicon labs ? factory data in code/xdata ram. this variable is set after the boot. user must read the variable to determine where is the end of the usable code/xdata ram mem- ory for user?s use. the address is stored in big endian fashion; address msb byte at the variable address loca- tion, followed by lsb byte on the next (address + 1) loca- tion. wboot_nvmuserbeg 0x11f5 word byte address of the first byte of the user load in the nvm memory. it is set by the factory load. the user load must start at that address in nvm. boot routine reads this vari- able before loading the user code after it finished loading the factory load. wboot_nvmcopyaddr 0x11fd word first unread data address in nvm by the nvm copy routine bnvm_copyblock . after the boot is done this variable contains, in big endian, the nvm address of the first nvm byte not read by nvm copy routine. this is the first ?empty? byte in nvm which is available for new data. the value of this variable is essential when the user wants to add more data to nvm later on. bboot_bootstat 0x11ff byte boot status. user program can read this byte and decide whether the boot finished correc tly. if not, then it can blink led or not to continue with running the code. see the bboot_bootstat bit description table. *note: word is an unsigned 16 bit value, byte is an unsigned 8 bit value.
rev. 1.0 77 SI4010-C2 xdata address = 0x11ff apart from the code/xdata ram memory region th ere is a boot control and status sfr register, boot_flags. it controls the end of the boot and has error status bit, which is set when bboot_bootstat variable has other than 0x00 value. that is added for convenience so the user code can just check a single bit in sfr register rather than reading xdata variable to determine whether boot finished successfully or not. if the bboot_bootstat xdata variable is not 0x00, the boot fail flag is set in the boot_flags sfr. the other bits control whet her the user code will run after the boot. if the debugging chain is used and user code is loaded through ide, this process is transpar ent to the user. whenever the ide connects to the device, it resets and halts the device, awaiting user. the user will generally not write to the boot_flags register. however, if the user wants to make the user part to behave as a factory part, then it is possible to write value 0x20 to the boot_flags register through id e (see view -> debug windows -> sfr -> boot window). don?t forg et to press the refresh ide button for the change to ta ke effect. then until the power to the part is cycled the part would behave as a factory part. xdata variable defini tion 24.1. bboot_bootstat bit76543210 name bs_gpio_ xtal reserved bs_err_factory[2:0] bs_err_ user_ next bs_err_ user_ first type rrr r rr reset 0/10000000 bit name function 7 bs_gpio_ xtal gpio0 read before boot. read gpio0 value at the very beginning of the boot prior to optionally turning on the xo (crystal oscillator). 6:5 reserved reserved. 4:2 bs_err_ factory [2:0] load of the factory data. load of the factory data failed if value is other than 0x0 1 bs_err_ user_ next load of the second or subsequent user block. load of the second or subsequent user block failed if other than 0. 0 bs_err_ user_ first load of the first user block. load of the first user block failed if other than 0.
SI4010-C2 78 rev. 1.0 sfr address = 0xdd sfr definition 24.2. boot_flags bit76543210 name reserved reserved boot_ trim_ por code_ run_ por reserved boot_ fail_ sys boot_ done_ sys code_ run_sys type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:6 reserved reserved. 5 boot_tri m_por force user part to act as a factory part. for user part only: during the boot process load only factory values and stop. by other words, act like a factory part. must be set for additional programming of the user part or for loading user test code to ram when the part is programmed as user part. this bit has higher priority then the prot3_ctrl.user_cont bit. 4 code_ run_ por run user code in ram. same functionality as code_run_sys. 3 reserved reserved. 2 boot_ fail_ sys boot loading process failed. this is an information flag, independent of the boot_d one_sys. this bit is set when the boot status xdata variable bboot_bootstat is not equal to 0x00, signal- ling error during boot. ? it is recommended that the user code reads this bit and possibly make decisions whether to continue with the execution of the loaded ram code, which might not be complete, or signal to a user a problem, by, for example, blinking led in some not- ordinary fashion. 1 boot_ done_ sys boot routine finished flag. always set to 1 at the end of the boot. 0 code_ run_sys run user code in ram. used for factory and user program states, igno red in run state. when this bit is set the boot routine will jump to code address 0x0000 . forced by the d ebugging chain if the device is connected to the ide.
rev. 1.0 79 SI4010-C2 24.9. boot routine d estination address space the boot process reads the formatted data from nvm and writes it to the desired destination. the format supports different address regions based on the dest ination (write) address. th e destination address is part of the nvm content data frame format. figure 24.3. boot routine destination cpu address space for copy from nvm the address space of the nvm image destinations depend on the program level of the chip and is shown in figure 24.3: ? 0x0000 .. 0x11ff .. code/xdata ram. the end of the ram is reserved for the boot control data. ? 0x7000 .. 0x70ff .. virtually mapped 256 byte of ir am for data/idata indirect access. whenever the destination address in the nvm imag e is in this region the data destination is going to be data/idata iram space. however, only region 0x7020 .. 0x70ef is writable. that means that the first 32 and last 16 bytes of the iram are not writable by a boot proc ess. note that the mapping is for indirect internal iram access (data/idata), so sfr register s cannot be initialized by this process. it is up to the user to generate intelhex files to be passed to the nvm programmer. the nvm programmer will ensure that the nvm gets program med with a proper data structures such that the data values pro- vided in the intelhex files will appear at the ram and iram addresses specified in the intelhex input file after the boot is done. 64kb 16kb 0x0000 ram 4.5k 0xffff 0x8000 0x4000 0x7000 iram 256b 0x11ff boot routine view of the cpu memory space for writing user data from the nvm to the ram/register spaces
SI4010-C2 80 rev. 1.0 note that by using the unified code/xdata memory and by mapping the iram to the boot process address space the user can initialize both xdata and iram variables directly from the user nvm load without the need for running any startup code to do variab le initializations, resultin g in the saving of a code size. one application of the data initializat ion by a boot process could be copy ing of keys from the nvm to fixed locations without any code intervention. the user c an program all the chips with the same application in the factory and then add only a very small, per chip, user block with keys, specifying where to the xdata and/or iram memories the boot process should copy the val ues of the keys. for example, to initialize iram location 0x56 to 0x a4 value the user will provid e and intelhex file specify- ing that at the address 0x7056 the data value should be 0xa4. 24.10. nvm programming the user program/data is stored in the nvm memory in a proprietary form; therefore, the nvm program- ming can be done only by the silicon labs provided co mposer and programmer ut ility. the data preparer will take user generated application intelhex files, us er settings (see below), an d will generate data to be programmed into the nvm. the nvm programmer then programs the data into the nvm. during the composing/ programming process the user will have control of the following: 1. make factory part a user part .. program user data into the nvm 2. update user part .. add additional user data block to the existing user data already in nvm. this process can be done many times as long as there is a space in nvm. 3. make user part a run part .. mark a part as a final mission mode part. when making the part a run part the user can decide whether the part retest will be allowed an d if so, then what protection restrictions the user is going to impose during the retest process. these steps can be combined into a single programmi ng step. step 2. is optional and is convenient when part specific data needs to be added later to the nvm load. to support the nvm progr amming silicon labs provides two utilities: ? nvm programming utility : the nvm configuration can be easily setup with this microsoft windows based gui. this application contains both the co mposer and burner functions. please check the application note an511:nvm prog ramming user guide for details ? command line nvm programming application: this app lication can be integrated into the customer's production line. this utility expects a composed nvm content file as an inpu t (created by the nvm programming utility). see the corresponding applicat ion note for details. in addition, 3rd party pr ogrammer support is availa ble for high-volume product ion programming. silicon labs can also program parts directly for customers for high-volume prod uction. contact your silicon labs representative for more details.
rev. 1.0 81 SI4010-C2 24.11. retest and re test configuration when the part is programmed as a run part, the c2 interface is disabled and nobody can access the part externally. however, silicon labs needs to be able to retest the part in case it returns as a failed part from a customer application. silicon lab s understands that customer may ha ve programmed sensitive informa- tion into the nvm which should not be revealed to anybody, not even to silicon labs, during the retest pro- cess. during the process of making the part a run part the user will have one time option to control the access to the chip durin g the retest process. to be able to retest the fully programmed run part, a special sequence of pin values needs to be applied at a particular time during the boot process. once th at sequence is recognized by the part, the boot pro- cess loads only the factory region of the nvm and will not load any of the user regions from the nvm. then before the boot process opens the c2 in terface for factory retest communi cation, it consults the user retest protection control flags programmed into the prot3_ctrl byte in nvm when the part was made a run part and acts on the values immediately. only afte r all the actions prescribed by the flags settings are completed can the chip open for retest communication. when making a run part, the user can set the following retest protection flags when using the nvm programmer. note that if the bits are set into the prot3_ctrl nvm byte be fore the part is programmed as run part (for example, those bits are set when making a user part), the settings are ignored. the boot process will monitor these values only after the part is programmed to be the run part. table 24.2. run chip retest protection flags: nvm programmer flag name description c2_off disable the c2 interface for good. no retest possible. ? warning : when set then the part is locked out, c2 interface is disabled forever, and silabs cannot retest the chip. there is no back door to the part. all other settings below are ignored, since they have no effect. ? ? this bit is set in prot0_ctrl.c2_off and it corresponds to c2 disable checkbox on the nvm programmer gui. mem_c2_prot protect code/xdata and iram ram memories. when set then the boot process clears code/xdata and iram ram's when the run chip is opened for retest. code/xdata and iram ram's get cleared with 0, excluding the factory region at the end of code/xdata. the iram gets also cleared completely outside of t he register bank 0 (bottom 8 registers). this ensures that there is no lingering user code or data values, like keys, in any of the ram?s. this bit is in prot3_ctrl.mem_c2_prot and it corresponds to ram clear checkbox on the nvm programmer gui.
SI4010-C2 82 rev. 1.0 once these options are programmed to the part they cannot be undone or changed. additional setting of these options after the part is made a run part is not possible either. mtp_c2_prot protect mtp. when set then both wr and rd access to mtp is disabled. forces boot process to set mtp_prot=1 to disable mtp communication completely. reading from mtp returns 0x00 values, writing is not possible. customer may want to set this option if there is a sensitive information written into the mtp eeprom during the lifetime of the part. this bit is in prot3_ctrl.mtp_c2_prot and it corresponds to mtp disable checkbox on the nvm programmer gui. nvm_c2_prot protect nvm. when set then both wr and rd access to nvm is disabled. it forces boot process to write nvm_prot=1 at the end of the boot process to disable nvm access. this protects user load in nvm from being read by silabs. if this option is used then the silabs can sti ll do the following with nvm content during retest: 1. calculate crc32 over the factory region of nvm. 2. calculate crc32 over the user portion of the nvm, which is the whole nvm excluding the factory region and the last 64 bytes of nvm. 3. read the end 64 bytes of the nvm, which is a reserved nvm region for silabs use. when this option is set then silabs cannot do anything else with nvm during retest. this bit is in prot3_ctrl.nvm_c2_prot and it corresponds to nvm disable checkbox on the nvm programmer gui. table 24.2. run chip retest protection flags: nvm programmer flag name description
rev. 1.0 83 SI4010-C2 24.12. boot and retest protection nvm control byte the boot process monitors the value of an nvm byte called prot3_ctrl . there is not a corresponding hardware register to this byte. it is a value in the factory region at the beginning of nvm. the register contains retest protection flags described above an d modification of the boot for user part. each bit is write 1 once. once the bit is programmed it cannot be cleared. the bits are programmable though the checkboxes in the nvm programmer. once the bit is set, there is no way to monitor the current status of the bit in the prot3_ctrl nvm byte on the device. nvm byte definition 24.3. prot3_ctrl bit76543210 name nvm_c2_ prot mtp_c2_ prot mem_c2_ prot boot_xo _ena reserved user_ cont reserved type w www r w r reset 0 000 0x0 0 0 bit name function 7 nvm_c2_ prot nvm protection (disable) when entering retest mode. this bit corresponds to nvm disable checkbox on the nvm programmer gui. 6 mtp_c2_pr ot mtp protection (disable) when entering retest mode. this bit corresponds to mtp disable checkbox on the nvm programmer gui. 5 mem_c2_ prot ram clearing (content protection) when entering retest mode. this bit corresponds to ram clear checkbox on the nvm programmer gui. 4 boot_xo_ ena enable the crystal oscillator (xo) at the beginning of the boot process. this is valid in any device programming level, including factory . since it can take up to 10ms for the xo to stabilize and about 3.6 ms to load 1 kb of data from nv m to ram, the user may decide to enable th e xo at the beginning of the boot process so the xo will be stabilizing while the device is going through the boot process to save time in the main application. this bit corresponds to xo early enable checkbox on the nvm programmer gui. 2:3 reserved reserved. 1 user_cont run the user code in user pa rt after boot automatically. for user programming level only, has no effect in other programming levels. normally when the part is programmed as user the user co de is loaded from nvm to ram, but is not executed automatically. if this bit is set, then the user load is executed automatically after boot. this bit corresponds to exe user boot checkbox on the nvm programmer gui. 0 reserved reserved.
SI4010-C2 84 rev. 1.0 24.13. chip protect ion control register the boot process sets the value of the devic e protection and configuration sfr register, prot0_ctrl . the user can read the register and check the programming level of the de vice as well as protections set to control access to the nvm and mtp memories and c2 interface. the register is user writable, but once a value of 1 is written to any of the bits in the register it cannot be written as 0. only cycling the power to the part clears the bits, but the boot process will set this r egister again to the value st ored in nvm. protections can only be made stronger, not weaker. writing to this register does not affect the underlying data located in nvm. sfr address = 0xda sfr definition 24.4. prot0_ctrl bit76 5 43 210 name nvm_ prot c2_off reserved mtp_ prot nvm_ wr_ prot nvm_blown[2:0] type r/w r/w r r/w r/w r/w r/w r/w reset 00 1 00 000 bit name function 7 nvm_ prot nvm protection. disable nvm access completely. neither read nor write to nvm is possible. write 1 sets the bit, write 0 has no effect. 6c2_off c2 interface disable. write 1 sets the bit, write 0 has no effect. this bit is reset by the main digital power on reset. power has to be cycled to reset this bi t or chip has to wake up from shutdown. if c2 is disabled then the chip is not accessible by a debug chain and not available for retest. 5 reserved reserved. 4 mtp_ prot mtp protection. disable mtp access. if set then mtp will be co mpletely disabled. all reads from mtp will be 0x00. write 1 sets the bit, write 0 has no effect. 3 nvm_ wr_ prot nvm write protection. if this bit is set the nvm is write protected. however, the value is used only if the chip program level is run, nvm_blown=3?b11x. in all other cases the value of this bit is ignored. 2:0 nvm_ blown [2:0] displays chip program level. the bits can only be set to 1, write 0 has no effect: 001 .. factory 011 .. user 111 .. run
rev. 1.0 85 SI4010-C2 25. on-chip registers there are two register regions on chip: ? special function registers region ? xreg region 25.1. special func tion registers the direct-access data memory locations from 0x80 to 0xff constitute the sp ecial function registers (sfrs). the sfrs provide control and data exchange with the SI4010-C2's resources and peripherals. the cip-51 controller core duplicates the sfrs found in a typical 8051 implementation as well as imple- menting additional sfrs used to configure and acce ss the sub-systems unique to the SI4010-C2. this allows the addition of new functi onality while retaining compatibility with the mcs-51? instruction set. table 25.2 lists the sfrs implemented in the SI4010-C2 device family. the sfr registers are accessed anytime the direct ad dressing mode is used to access memory locations from 0x80 to 0xff. sfrs with addresses ending in 0x0 or 0x8 (e.g. p0, p1, acc, ie, etc.) are bit-address- able as well as byte-addressable. all other sfrs are byte-addressable only. unoccupied addresses in the sfr space are reserved for future use. accessing these areas will have an indetermi nate effect and should be avoided. refer to the corresponding pages of the data sheet, as indicated in table 25.2, for a detailed description of each register. table 25.1. special function register (sfr) memory map 0x80 0x90 0xa0 0xb0 0xc0 0xd0 0xe0 0xf0 0* p0* p1* p2* psw* acc* b* 1 sp gpr_ctrl 2 dpl gpr_data 3 dph 4 gfm_data p0con lc_fsk 5 gfm_const p1con port_ctrl 6 sbox_data port_set eie1 eip1 7 pcon port_intcfg 8* ie* ip* tmr2ctrl* 9 rbit_data ods_ctrl tmr3ctrl tmr_clksel a ods_timing tmr3rl tmr2rl prot0_ctrl b fc_ctrl ods_data tmr3rh tmr2rh c rtc_ctrl ods_ratel tmr3l tmr2l d fc_interval ods_rateh tmr3h tmr2h boot_flags e ods_warm1 sysgen pa_lvl sys_set f clkout_set ods_warms2 int_flags *notes: bit addressable registers.
SI4010-C2 86 rev. 1.0 table 25.2. special function registers sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page acc 0xe0 accumulator 62 b 0xf0 b register 63 boot_flags 0xdd boot flags 78 clkout_set 0x8f clock output settings 124 dph 0x83 data pointer high 61 dpl 0x82 data pointer low 61 eie1 0xe6 extended interrupt enable 1 96 eip1 0xf6 extended interrupt priority 1 97 fc_ctrl 0x9b frequency counter control 52 fc_interval 0x9d frequency counter interval 53 gfm_const 0x85 aes gfm multiplier constant 104 gfm_data 0x84 aes gfm data 104 gpr_ctrl 0xb1 general purpose control register 126 gpr_data 0xb2 general purpose data register 126 ie 0xa8 interrupt enable 94 ip 0xb8 interrupt priority 95 int_flags 0xbf interrupt flags 98 lc_fsk 0xe4 lc fsk deviation 46 ods_ctrl 0xa9 ods control 41 ods_data 0xab ods data 43 ods_rateh 0xad ods rate high byte 44 ods_ratel 0xac ods rate low byte 43 ods_timing 0xaa ods timing register 42 ods_warm1 0xae ods warm up times for pa and divider 44 ods_warm2 0xaf ods warm up time for lcosc 45 p0 0x80 port 0 latch 118 p0con 0xa4 port 0 configuration 119 p1 0x90 port 1 latch 119 p1con 0xa5 port 1 configuration 120 p2 0xa0 port 2 latch 120 pa_lvl 0xce power amplifier level 38 pcon 0x87 power control 102 port_ctrl 0xb5 port control 121
rev. 1.0 87 SI4010-C2 port_intcfg 0xb7 port interrupt configuration 100 port_set 0xb6 port set 122 prot0_ctrl 0xda protection 0 control 84 psw 0xd0 program status word 64 rbit_data 0x99 read bit data 127 rtc_ctrl 0x9c real time clock control 130 sbox_data 0x86 aes sbox data 105 sp 0x81 stack pointer 62 sysgen 0xbe system gene rator register 48 sys_set 0xee system setup register 105 tmr2ctrl 0xc8 timer/counter 2 control 140 tmr2h 0xcd timer/counter 2 high 143 tmr2l 0xcc timer/counter 2 low 143 tmr2rh 0xcb timer/counter 2 reload high 142 tmr2rl 0xca timer/counter 2 reload low 142 tmr3ctrl 0x91 timer/counter 3control 144 tmr3h 0x95 timer/counter 3 high 147 tmr3l 0x94 timer/counter 3low 147 tmr3rh 0x93 timer/counter 3 reload high 147 tmr3rl 0x92 timer/counter 3 reload low 146 tmr_clksel 0xc9 timer source clock selection 139 table 25.2. special function registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved register address description page
SI4010-C2 88 rev. 1.0 25.2. xreg registers the chip contains another set of registers implemented in the xreg memory area. these registers are located in the xdata address space, addressable by movx instructions only. from cpu perspective it is a regular external memory. the advantage of the xreg registers is that they ar e viewed by the cpu as a regular memory. therefore, they can be declared as different data types, structures, array of bytes, and so on. with sfr we only have special registers and it is not possible to declare them as long integers, for example. on the other hand the sfr register access is faster and one can use arithmetic and logical operations on them. note registers in the xreg regions are aligned at 8, 16, and 32 bit boundaries and they are stored in big endian fashion. this is to su pport keil c compiler, which uses big endian . note that if the register is, say 23 bits wide, the 32 bits (4 bytes) are allocated for the register and the register is aligned in big endian fashion. therefore, th e lsb byte of the regist er will be at the address + 3, while the byte directly at the is the msb byte and is empty (read as 0x0), si nce the register itself is only 23 bits wide. table 25.3 shows a memory map of the xreg registers in the external memory space.
rev. 1.0 89 SI4010-C2 table 25.3. xreg register memory map in external memory xdata address type name byte order 0x4002 byte blposc_trim msb byte lsb byte msb byte lsb byte byte [0] byte [15] 0x4003 ... 0x4007 0x4008 0x4009 0x400a 0x400b lword ifc_count 0x400c 0x400d word wpa_cap 0x400e ... 0x4011 0x4012 byte bpa_trim 0x4013 ... 0x4015 0x4016 byte bxo_ctrl 0x4017 byte bport_tst 0x4018 ... 0x4026 0x4040 ... 0x404f byte abmtp_rdata[16] note: multiple byte variables, if they are not arrays, are stored in big endian .. ? msb byte stored on lower address. arrays are stored with byte index [0] at lower address.
SI4010-C2 90 rev. 1.0 description of the xreg register fields on the previ ous pages includes only the used register bits. the fields are aligned towards the lsb byte of the xreg register. if the actual xreg register is wider then the field described the missing bits towards msb byte are all read as 0's and writing to them has no effect. for example, the register wpa_cap contains a single 9 bit fi eld. since it is more than 8 bits and less then 16 it occupies two bytes. that's why the prefix letter 'w' den oting a two byte word. the bits [15:9] are read as all zeros and write has no effect. they are aligned towards msb byte of the wpa_cap, the one at lower address since the byte ordering is in big endian fashion. table 25.4. xreg registers xregs are listed in alphabetical order. register address description page lfc_count 0x4008 frequency counter output 53 blposc_trim 0x4002 low power oscillator trim 47 abmtp_rdata[16] 0x4040 mtp_read data bytes 68 wpa_cap 0x400c pa variable capacitor 38 bpa_trim 0x4012 pa max drive bit 39 bxo_ctrl 0x4016 xo control 49
rev. 1.0 91 SI4010-C2 26. interrupts the si4010 device includes an extended interrupt system supporting a total of 12 interrupt sources with two priority levels. each interrupt source has one or more associated interrupt-pending flag(s) located in an sfr. when a peripheral or external source meets a valid interrupt condition, the associated interrupt- pending flag is set to logic ?1?. if interrupts are enabled for the source, an interrupt req uest is generated when the interrupt-pending flag is set. as soon as execution of the current instructio n is complete, the cpu generates an lcall to a prede- termined address to begin execution of an interrupt se rvice routine (isr). each isr must end with an reti instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. if interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal. th e interrupt-pending flag is set to logic ?1? regard- less of the interrupt's enable/disable state. each interrupt source can be individually enabled or disabled through the use of an associated interrupt enable bit in the interrupt enable and extended interrupt enable sfrs. however, interrupts must first be globally enabled by setting the ea bit (ie.7) to logic ?1? before the individual interrupt enables are recog- nized. setting the ea bit to logic ?0? disables all interrupt sour ces regardless of the individual interrupt-enable set- tings. note that interrupts which occur when the ea bit is set to logic ?0? will be held in a pending state, and will not be serviced until the ea bit is set back to logic ?1?. note: any instruction that clears a bit to disable an inte rrupt should be immediatel y followed by an instruc- tion that has two or more opcode bytes. using ea (global interrupt enable) as an example: // in 'c': ea = 0; // clear ea bit. ea = 0; // this is a dummy instruction with two-byte opcode. ; in assembly: clr ea ; clear ea bit. clr ea ; this is a dummy instruction with two-byte opcode. for example, if an interrupt is posted during the exec ution phase of a "clr ea" opcode (or any instruction which clears a bit to disable an interrupt source), an d the instruction is followed by a single-cycle instruc- tion, the interrupt may be taken. however, a read of the enable bit will return a '0' inside the interrupt ser- vice routine. when the bit-clearing op code is followed by a multi-cycle in struction, the interrupt will not be taken. on this device no interrupt-pending flags are automa tically cleared by the hardware when the cpu vectors to the isr. the flags must be cleared by software before returning from the isr. if an interrupt-pending flag remains set after the cpu completes the return-from-interrupt (reti) instruction, a new interrupt request will be generated im mediately and the cpu will re-enter the isr after the completion of the next instruction.
SI4010-C2 92 rev. 1.0 26.1. mcu interrupt sources and vectors the device supports 12 interrupt sources. software can simulate an interrupt by setting any interrupt-pend- ing flag to logic ?1?. if interrupts are enabled for th e flag, an interrupt reques t will be generated and the cpu will vector to the isr address associ ated with the interrup t-pending flag. mcu inte rrupt sources, associ- ated vector addresses, priority order, and control bi ts are summarized in table 26.1. refer to the data sheet section associated with a particular on-chip peri pheral for information regarding valid interrupt condi- tions for the peripheral and the behavior of its interrupt-pending flag(s). 26.2. interrupt priorities each interrupt source can be individually programmed to one of two priority levels: low or high. a low prior- ity interrupt service routine can be pree mpted by a high priority interrupt. a high priority interrupt cannot be preempted. each interrupt has an associated interrupt priority bit in an sfr (ip or eip1) used to configure its priority level. low priority is th e default. if two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. if both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in table 26.1. 26.3. interrupt latency interrupt response time depends on the state of the cpu when the interrupt occurs. pending interrupts are sampled and priority decoded each sys tem clock cycle. therefore, the fa stest possible response time is 5 system clock cycles: 1 clock cycle to detect the interr upt and 4 clock cycles to complete the lcall to the isr. additional clock cycles will be required if a chace miss occurs. if an interrupt is pending when a reti is executed, a single instruction is executed before an lcall is made to service the pending interrupt. therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new interrupt is of greater priority) is when the cpu is performing an reti instruction followed by a div as the next instruction. if the cpu is executing an isr for an interrupt with equal or higher priority, the new interrupt will not be serv iced until the current isr completes, including the reti and following instruc- tion.
rev. 1.0 93 SI4010-C2 26.4. interrupt re gister descriptions the sfrs used to enable the interrupt sources and set their priority level are described in this section. refer to the data sheet section associated with a pa rticular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). table 26.1. interrupt summary interrupt source interrupt vector priority order pending flag bit addressable? enable flag priority control reset 0x0000 top none n/a always enabled always highest external int 0 (int0 ) 0x0003 0 int0_flag (int_flags.0) n eint0 (ie.0) pint0 (ip.0) timer 2 overflow 0x000b 1 tmr2intl (tmr2ctrl.6) tmr2inth (tmr2ctrl.7) yetmr2 (ie.1) ptmr2 (ip.1) temp sensor dmd 0x0013 2 dmd_new (dmd_ctrl.3) n edmd (ie.2) pdmd (ip.2) real time clock tick 0x001b 3 rtc_int (rtc_ctrl.7) n ertc (ie.3) prtc (ip.3) ods ready for data 0x0023 4 ods_flag (int_flags.2) n eods (ie.4) pods (ip.4) timer 3 overflow 0x002b 5 tmr3intl (tmr3ctrl.6) tmr3inth (tmr3ctrl.7) netmr3 (ie.5) ptmr3 (ip.5) external int1 0x0033 6 int1_flag (int_flags.1) n eint1 (ie.6) pint1 (ip.6) reserved 0x003b 7 n/a n/a n/a n/a reserved 0x0043 8 n/a n/a n/a n/a frequency counter count done 0x004b 9 fc_done (fc_ctrl.7) nefc (eie1.2) pfc (eip1.2) software source 0 ? (can be used for software generated interrupts) 0x0053 10 void0_flag (int_flags.3) n evoid0 (eie1.3) pvoid0 (eip1.3) software source 1 ? (can be used for software generated interrupts) 0x005b 11 void1_flag (int_flags.4) n evoid1 (eie1.4) pvoid1 (eip1.4)
SI4010-C2 94 rev. 1.0 sfr address = 0xa8; bit-addressable sfr definition 26.1. ie bit76543 2 10 name ea eint1 etmr3 eods ertc edmd etmr2 eint0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000 0 00 bit name function 7ea enable all interrupts. globally enables/disables all interrupts. it overrides individual interrupt mask settings. 0: disable all in terrupt sources. 1: enable each interrupt accordi ng to its individual mask setting. 6eint1 enable external edge interrupt 1. this bit sets the masking of external interrupt 1. 0: disable external interrupt 1. 1: enable interrupt requests generated by the int1 input. 5etmr3 enable timer 3 interrupt. this bit sets the masking of the timer 3 interrupt. 0: disable timer 3 interrupt. 1: enable interrupt requests generated by the tf3l or tf3h flags. 4eods enable output data serializer interrupt. this bit sets the masking of the ods interrupt. 0: disable ods interrupt. 1: enable ods interrupt. 3ertc enable real time clock interrupt. this bit sets the masking of the rtc interrupt. 0: disable all rtc interrupt. 1: enable rt c interrupt. 2edmd enable dmd (ts demodulator). this bit sets the masking of the dm d interrupt. 0: disable dmd interrupt. 1:enable dmd interrupt. 1etmr2 enable timer 2 interrupt. this bit sets the masking of the timer 2 interrupt. 0: disable all timer 2 interrupt. 1: enable interrupt requests generated by the tf2 flag. 0eint0 enable external edge interrupt 0. this bit sets the masking of external interrupt 0. 0: disable external interrupt 0. 1: enable interrupt requests generated by the int0 input.
rev. 1.0 95 SI4010-C2 sfr address = 0xb8; bit-addressable sfr definition 26.2. ip bit76543 2 10 name reserved pint1 ptmr3 po ds prtc pdmd ptmr2 pint0 type r/w r/w r/w r/w r/w r/w r/w r/w reset 10000 0 00 bit name function 7 reserved read = 1, write = don't care. 6pint1 external edge interrupt 1 priority control. this bit sets the priority of the external interrupt 1 interrupt. 0: external interrupt 1 se t to low priority level. 1: external interrupt 1 se t to high priority level. 5ptmr3 timer 3 interrupt priority control. this bit sets the priority of the timer 3 interrupt. 0: timer 3 interrupt set to low priority level. 1: timer 3 interrupt set to high priority level. 4pods output data serializer interrupt priority control. this bit sets the priority of the ods interrupt. 0: ods interrupt set to low priority level. 1: ods interrupt set to high priority level. 3prtc real time clock interrupt priority control. this bit sets the priority of the rtc interrupt. 0: rtc interrupt set to low priority level. 1: rtc interrupt set to high priority level. 2pdmd dmd (ts demodulator) interrupt priority control. this bit sets the priority of the dmd interrupt. 0: dmd interrupt set to lower priority. 1: dmd interrupt set to higher priority. 1ptmr2 timer 2 interrupt priority control. this bit sets the priority of the timer 2 interrupt. 0: timer 2 interrupt set to low priority level. 1: timer 2 interrupt set to high priority level. 0pint0 external edge interrupt 0 priority control. this bit sets the priority of the external interrupt 0 interrupt. 0: external interrupt 0 se t to low priority level. 1: external interrupt 0 se t to high priority level.
SI4010-C2 96 rev. 1.0 sfr address = 0xe6 sfr definition 26.3. eie1 bit765432 1 0 name reserved reserved reserved evoid1 evoid0 efc reserved reserved type rrrr/wr/wr/wr r reset 000000 0 0 bit name function 7:5 reserved read as 0x0. write has no effect. 4evoid1 enable void1 interrupt (reserved). this bit sets the void1 interrupt.(reserved) 0: disable void1 interrupts. 1: enable interrupt requests gener ated by void1 flags (reserved). 3evoid0 enable void0 interrupt (reserved). this bit sets the void0 interrupt.(reserved) 0: disable void0 interrupts. 1: enable interrupt requests gener ated by void0 flags (reserved). 2efc enable frequency counter interrupt. this bit sets the frequency counter interrupt. 0: disable frequency counter interrupt. 1: enable interrupt requests generated by frequency counter. 1:0 reserved reset value 0x0 must not be changed.
rev. 1.0 97 SI4010-C2 sfr address = 0xf6 sfr definition 26.4. eip1 bit76543210 name reserved pvoid1 pvoid0 pfc reserved type r r/w r/w r/w r/w reset 0 000 0 bit name function 7:5 reserved read as 0x0. write has no effect. 4pvoid1 void1 interrupt priority control. this bit sets the priority of the void1 interrupt. 0: void1 interrupt set to low priority level. 1: void1 interrupt set to high priority level. 3pvoid0 void0 interrupt priority control. this bit sets the priority of the void0 interrupt. 0: void0 interrupt set to low priority level. 1: void0 interrupt set to high priority level. 2pfc frequency counter interrupt priority control. this bit sets the priority of the frequency counter interrupt. 0: frequency counter interrup t set to low priority level. 1: frequency counter interrupt set to high priority level. 1:0 reserved reset value 0x0 must not be changed.
SI4010-C2 98 rev. 1.0 sfr definition 26.5. int_flags sfr address = 0xbf bit76543210 name reserved reserved reserved void1_ flag void0_ flag ods_ flag int1_ flag int0_ flag type r r r r/w r/w r/w r/w r/w reset 00000000 bit name function 7:5 reserved read as 0x0. write has no effect. 4 void1_ flag spare interrupt flag (can be used freely by the user application software). interrupt can be invoked by soft ware only by writing 1 here. 3 void0_ flag spare interrupt flag (can be used freely by the user application software). interrupt can be invoked by soft ware only by writing 1 here. 2 ods_ flag set when tx data holding register becomes empty. it must be cleared by software before writing a new byte into the ods tx data register. hardware will not clear this bit. 1 int1_ flag set by selected gpio input by a selected edge. it gets set irrespective of the eint0 setting. it must be cleared by software. hard- ware will not clear this bit. 0 int0_ flag set by selected gpio input by a selected edge. it gets set irrespective of the eint0 setting. it must be cleared by software. hard- ware will not clear this bit.
rev. 1.0 99 SI4010-C2 26.5. external interrupts the int0 and int1 external interrupt sources are configurable as active high or low. they are edge sensi- tive only, not level sensitive. these are not the same int0 and int1 as found on original 8051 architecture. each of the int0 and int1 can invoke interrupt on the rising edge, falling edge, or both edges of the selected gpio pins associated wit h the int0 and int1, respectively. the single edge or double edge feature is contro lled by the edge_int0 and edge_int1 bits in the port_set register. the edge polarity is defined in the port_intcfg register. int0 and int1 are assigned to port pins as define d in the port_intcfg register. note that the corre- sponding pending flag for int0 or int1 is not automatically cleared by the hardware when the cpu vec- tors to the isr. this is a departure from the original 8051 architecture where if external interrupts were configured to be edge sensitive the corresponding inte rrupt flag was cleared by hardware upon the exit from the isr routine. the detection of the edges of int0 and int1 sources is done by sampling the associated port inputs by the internal system clock. therefore, th e edge detector will miss pulses shor ter than 2 periods of the internal system clock periods. note that the in ternal system clock frequency is programmable and can be as low as 24 mhz/128. it is up to the user to recognize possi ble external interrupt delays associated with sampling of the int0 and int1 by the system clock at the current, user selected, clock frequency. the int1 and int0 internal signals are also used as capture event signals for timer 3 and 2, respectively, if they are running in capture mode.
SI4010-C2 100 rev. 1.0 sfr address = 0xb7 sfr definition 26.6. port_intcfg bit76543210 name neg_ int1 sel_int1[2:0] neg_ int0 sel_int0[2:0] type r/w r/w r/w r/w reset 00000000 bit name function 7 neg_ int1 negative int1 polarity. this bit selects whethe r the selected int1 gpio input will get inverted or pass as is before going to the edge detector. note the edge detector detects either the rising edge or both. the mode is selectable by edge_int1 bit is separate register. 0: pass the selected gpio unchanged. 1: inverts the selected gpio. 6:4 sel_ int1[2:0] int1 port pin selection bits. these bits select which port pin is assigned to int1. 000: select gpio0 001: select gpio1 010: select gpio2 011: select gpio3 100: select gpio4 101: select gpio9 110: select gpio6 111: select gpio7 3 neg_ int0 negative int0 polarity. this bit selects whethe r the selected int0 gpio input will get inverted or pass as is before going to the edge detector. note the edge detector detects either the rising edge or both. the mode is selectable by edge_int0 bit is separate register. 0: pass the selected gpio unchanged. 1: inverts the selected gpio. 2:0 sel_ int0[2:0] int0 port pin selection bits. these bits select which port pin is assigned to int0. 000: select gpio0 001: select gpio1 010: select gpio2 011: select gpio3 100: select gpio4 101: select gpio8 110: select gpio6 111: select gpio7
rev. 1.0 101 SI4010-C2 27. power management modes the cip-51 core has two software programmable power management modes: idle and stop . idle mode halts the cpu while leaving the external pe ripherals and internal clocks active. in stop mode, the cpu is halted, all interrupts and timers are inactive. the system clock is still running when the cpu is in stop mode. since clocks are running, power consumption is dependent upon the system clock frequency and the number of peripherals left in active mode before entering idle or stop . see the sfr definition of the power control register (pcon) used to control the cpu power management modes. although the cip-51 has idle and stop modes built in (as with any standard 8051 architecture), power management of the entire mcu is better accomplished by enabling/disabling individual peripherals as needed. each analog peripheral can be disabled when not in use and put into low power mode. digital peripherals, such as timers, draw little power whenever they are not in use. the devices feature an additional shutdown mode, whic h shuts the device down. the device then can be woken up by pulling gpio input to ground. see other sections for details. 27.1. idle mode setting the idle mode select bit (pcon.0) causes the cip-51 to halt the cpu and enter idle mode as soon as the instruction that sets the bit completes. all internal registers and memory maintain their original data. all analog and digital peripherals can remain active during idle mode. idle mode is terminated when an enabled interrupt or re set is asserted. the assertion of an enabled inter- rupt will cause the idle m ode selection bit (pcon.0) to be cleared and the cpu to resume operation. the pending interrupt will be serviced and the next instru ction to be executed after the return from interrupt (reti) will be the instruction im mediately following the one that se t the idle mode select bit. if idle mode is terminated by an external reset, the cip-51 performs a normal reset sequence. note: any instruction which sets the idle bit should be immediately followed by an instruction which has two or more opcode bytes. for example: in c: pcon |= 0x01; // set idle bit pcon = pcon; // ... followed by a 3-cycle dummy instruction; in assembly: orl pcon, #01h ; set idle bit mov pcon, pcon ; ... followed by a 3-cycle dummy instruction if the instruction following the write to the idle bit is a single-byte instru ction and an interrupt occurs during the execution of the instruction of th e instruction which sets the idle bit, the cpu may not wake from idle mode when a future interrupt occurs. 27.2. stop mode setting the stop mode select bit (pcon.1) causes the cip-51 to enter stop mode as soon as the instruc- tion that sets the bit completes. in stop mode, the cpu is stopped, effectively shutting down all digital peripherals. each analog peripheral must be shut down individually prior to entering stop mode. stop mode can only be terminated by an external rese t. on reset, the cip-51 performs the normal reset sequence and begins program execution based on the program level of the chip. the system clock is not stopped when in stop mode.
SI4010-C2 102 rev. 1.0 sfr address = 0x87 sfr definition 27.1. pcon bit76543210 name gf[5:0] stop idle type r/w r/w r/w reset 00000000 bit name function 7:2 gf[5:0] general purpose flags 5?0. these are general purpose flags for use under software control. 1stop stop mode select. setting this bit will place the cip-51 in st op mode. this bit will always be read as 0. 1: cpu goes into stop mode (internal oscillator stopped). 0idle idle mode select. setting this bit will place the cip-51 in idle mode. this bit will always be read as 0. 1: cpu goes into idle mode. (shuts off clo ck to cpu, but clock to timers, interrupts, serial ports, and analog peripherals are still active.)
rev. 1.0 103 SI4010-C2 28. aes hardware accelerator the device implements the aes (adv anced encryption st andard) hardware accelera tor. it is not a full hardware solution. the ha rdware accelerator is used by the s ilicon labs api firmware to implement aes 128 bit encrypt/decrypt functions. if the user wants to implement pr oprietary aes implementation in firm- ware it is possible to use the aes hardware accelerator. the accelerator has two parts: 1. aes galois field (gf) hardware multiplier 2. aes sbox/inverse sbox hardware module the galois field multiplier is desi gned to multiply two aes galois fiel d 8-bit elements, even though the aes just multiplies values by a constan t. it is up to the firmware to setu p the constant and data to multiply. the hardware implements efficient sbox/inverse sbox data processing. consult the aes standard for details. 28.1. aes sfr registers there are three sfr re gisters associated wit h the aes accelerator. to use the gf multiplier the user mu st first write the gfm_co nst register. the write is needed only if the user desires to change the previous value in that regist er. it holds its value until overwritten. to perform the multiply operation the data has to be written to gfm_data register. writing data to gfm_data register invokes the actual multiply operatio n. it takes 2 system clock cycles to perform the multiplication and the calculated result appears in the gfm_data register, ov erwriting the user input data. therefore, at least a single cycle dummy instruction must be added in be tween writing the data to be multiplied to the gfm_data register and reading the result from there: mov gfm_data, #data ; invoke a gf multiply nop ; at least single cycle wait instruction mov a, gfm_data ; read the result usage of the sbox/inverse sbox ha rdware is controlled by the aes_ decrypt bit in the sys_set regis- ter (sys_set.3). for enc ryption, the sbox operation is selected, for decrypti on the invers e sbox opera- tion is selected. to pass data through the sbox the user has to write the data to the sbox_data register. writing data there invokes the conversion operation. the result a ppears in the sbox_data register, overwriting the original data. it takes 2 system clock cycles to perform the conversion. therefore, at least a single cycle dummy instruction must be added in between writing th e data to be converted to the sbox_data register and reading the result from there: mov sbox_data, #data ; invoke a sbox conversion nop ; at least single cycle wait instruction mov a, sbox_data ; read the result if the silicon labs device api aes implementation is us ed by the user applicatio n, all the aes accelerator communication is handled by the api functions and is hidden from the user.
SI4010-C2 104 rev. 1.0 sfr definition 28.1. gfm_data sfr address = 0x84 sfr definition 28.2. gfm_const sfr address = 0x85 bit7654321 0 name gfm_data[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0000000 0 bit name function 7:0 gfm_data [7:0] gfm multiplier data processing. writing of a value here registers the data for processing. processed data is regis- tered into the same register with single clk_sys cycle delay. read from this reg- ister reads the processed multiplied data. the register gfm_const must be written before gfm_ data is written. bit7654321 0 name gfm_const[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0000000 0 bit name function 7:0 gfm_const [7:0] gfm multiplier constant register. this is the constant by which the gfm_da ta is multiplied by. it has to be written prior to gfm_data.
rev. 1.0 105 SI4010-C2 sfr definition 28.3. sbox_data sfr address = 0x86 sfr definition 28.4. sys_set sfr address = 0xee bit7654321 0 name sbox_data[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0000000 0 bit name function 7:0 sbox_data [7:0] aes sbox processing. writing of a value here registers the data for processing. processed data is regis- tered into the same register with single clk_sys cycle delay. read from this reg- ister reads the processed data. the type of sbox processing is controlled by aes_decrypt bit bit 7 6 5 4 3 2 1 0 name reserved reserved reserved reserved aes_decrypt reserved reserved reserved type r/w r/w r/w r/w r/w r/w r/w r/w reset 0001 0 000 bit name function 7:5 reserved reserved. read as 0x0. write has no effect. 4 reserved reserved. do not write to this bit. aes_decrypt aes sbox hardware logic control. 0: sbox is set for encryption. 1: sbox is set for decryption. reserved reserved. do not change these values.
SI4010-C2 106 rev. 1.0 29. reset sources reset circuitry allows the controller to be easily placed in a predefined default condition. there is only one external reset source for the device, which is po wer on reset. it gets invoked at two occasions: 1. power is supplied to the device. this means connecting the power supply to disconnected device or cycling the external power to the device. 2. the device is waking up from a shutdown/standby mode. the power supply was connected before, but the device was put into the shutdown/standby mode. the wake up event can happen because of two reasons: ? ? - one of the gpios is pulled low (e.g., a push button is pressed). ? - the (previously enabled) sleep timer is expired. on entry to the reset state, the following events occur: ? cip-51 halts program execution ? special function registers ( sfr ) are initialized to thei r defined reset values ? xdata registers ( xreg ) are initialized to their defined reset values ? external port pins are forced to a known state ? interrupts and timers are disabled ? all sfrs are reset to the predefined values noted in the sfr detailed descriptions. the contents of internal data memory is lost since the power got cycled. the port i/o latches are reset to 0xff (all logic ones) in open-drain mode. on exit from the reset state, the program counter (pc) is reset, and the system clock defaults to the inter- nal oscillator frequency of 24 mhz. device starts its startup boot proc edure. see other sections for descrip- tion of the boot procedure. the user code starts bei ng executed only after the boot procedure finishes. see section 24. system boot and nvm programming for details. 29.1. device boot outline since the device does not have flas h memory to permanently hold user code, the device has to go through a boot sequence in which the user code is copied from the one time programmable nvm memory to the code/xdata ram. after that is done the user program execution starts at address 0x0000. it takes about fixed 2 ms plus about 3.6 ms per 1 kb of user data to be copied from nvm to ram. when the user puts the device into shutdown mode this will be the estimated time for waking up the chip from shutdown mode by applying any gpio to ground and the ex ecution of the first instruction of the user code in code/xdata ram. for debugging purposes the user will not program the nvm, but will use the ram for code development. in that case the device will go through mu ch shorter startup routine, which w ould take less than 2 ms to con- clude. see ?24. system boot and nvm programming? on page 69 for details. 29.2. external reset there is no external reset. there is no pin dedicated to the device reset. the silicon labs debug chain using usb debug adapter or toolstick has access to the proprietary reset control on chip to facilitate user code debug and development. during the debugging sessions on unprogrammed part the content of the code/xdata ram is preserved in between ide environment invoked resets ( reset button inside ide).
rev. 1.0 107 SI4010-C2 29.3. software reset there is no traditional software reset on the si4010, bu t a similar result can be achieved by setting up the sleep timer and then putting the device into shutdown mode. this action effective disconnects power to the internal systems of the device. on ce the sleep time expires it will wake the si4010, which will have the same effect as a power on reset to the device creating a software reset. note that the sleep timer must be programmed and armed before the user puts the devices into shutdown mode.
SI4010-C2 108 rev. 1.0 30. port input/output digital resources are available through up to 10 i/o pins. the number of i/o depends on the package: ? 10 pin package .. 6 port pins organized as 6 bottom bits of port 0. ? 14 pin package .. 10 port pins organized as a fu ll 8-bit port 0 and 2 bottom bits of port 1. ? the package pin assignment is in figure 30.1. figure 30.1. device package and port assignments 8 9 10 11 12 13 14 7 6 5 4 3 2 1 gd txm txp vdd 10 pin package gpio[9] gpio[0]/ xo vpp gpio[7] gpio[1] matdrv / roff gpio[2] matdrv / roff gpio[3] matdrv gpio[4] c2dat gpio[5]/ led c2clk gpio[6] gpio[8]
rev. 1.0 109 SI4010-C2 pin assignments for 10? and 14?pin packages are shown in table 30.1 and table 30.2. the gpio port i/o can be configured as either open-drain or push-pull in sfr registers p0con and p1con. the gpio functional diagrams and related digi tal control are in figure 30.2 and figure 30.3. the option for matrix mode is available only on gpio[3 :1] and the option for roff mode is available only on gpio[2:1]. table 30.1. 10?pin mode package pin number package pin name 1 gpio0/xo 10 gpio1 9gpio2 8gpio3 7gpio4 6 gpio5/led table 30.2. 14?pin mode package pin number package pin name 2 gpio0/xo 13 gpio1 12 gpio2 11 gpio3 10 gpio4 9 gpio5/led 8gpio6 7gpio7 14 gpio8 1gpio9
SI4010-C2 110 rev. 1.0 figure 30.2. gpio[3:1] functional diagram functional diagram of the other gpio ports is in figure 30.3. it is th e general gpio circuit that can be forced by digital control to have limited functionality (e.g., as input only, etc.). figure 30.3. other gpio functional diagram vcc gpio[n] gpio_dataout[n] gpio_push_pull[n] gpio_in[n] port_dataout[n] port_oe[n] port_push_pull[n] gpio pads digital logic rd: port_matrix rd: port_roff e e 2 3 2 port_strobe wr: port_roff wr: port_matrix ~50k 1 vcc gpio[n] gpio_dataout[n] gpio_push_pull[n] gpio_in[n] port_dataout[n] port_oe[n] port_push_pull[n] gpio pads digital logic ~50k
rev. 1.0 111 SI4010-C2 30.1. gpio pin special roles not all gpio ports can be configured as both input and outputs. given the limited number of gpio each pin can assume different functionality based on the softwa re configuration of the po rts. the functionality of each gpio is described in table 30.3. it is important to em phasize the following: ? gpio[0] can be used only as input fo r user application. it can also serve as a crystal oscillator input. during device nvm programming the programming vpp=6.5v voltage is applied to this pin. ? gpio[5] can be used only as a up to 1ma led current driver. the led should be connected directly in between the gpio[5] and vcc. in a development system this pin is used as a c2 interface c2clk. in the development system the led has to be isolated from the pin as shown in figure 35.1 and figure 35.2 . the led is disabled during debugging. table 30.3. gpio special roles gpio number other special roles c2 fob can drive low during sleep pullup roff option 0 xo/vpp1 1 button 1buttonyy 2buttonyy 3 clk_ref 2 button y 4 clk_out out c2dat button 5 c2clk led 3 6 (14 pin only) clk_out out 4 button 7 (14 pin only) button 8 (14 pin only) button 9 (14 pin only) button notes: 1. can be set as gpio input only. special roles are crystal o scillator (xo) and vpp=6.5v nvm programming voltage supply during nvm programming. 2. reference clock source for frequency counter. 3. current mode driver for led connected directly to vcc supply. gpio[5] cannot be used for any other purpose in user application. 4. optional customer clock clk_out output can be set independently on gpio[4] and gpio[6], or on both at the same time.
SI4010-C2 112 rev. 1.0 30.2. pullup roff option there is an option to disable the weak pu llup pad resistors. this feature is called roff option. the roff option is controlled directly by the gpio pads and persist when the chip is in the shutdown mode. control of the roff control bit in the gpio is described in sectio n 30.4. pullup roff and matrix mode option con- trol. 30.3. matrix mode option the target application of the device is the button inte nsive application, which samples button pushes at the device inputs and acts accordingly. given the pin limited package, the target user application could use at most 5 buttons on a 10-pin package and 9 buttons on 14-pin package. if the chip is in a shutdown mode, any button push (connection to any gpio to ground) wakes the chip up. for the applications requiring more push butt on inputs than the available gpio inputs, matrix button mode should be implemented on the device. this allows th e buttons to be organized in 3x2 matrix for 10 pin package or 3x6 matrix for the 14-pin package, allowing for up to 6 push buttons for 10 pin package and up to 18 buttons on the 14-pin package. it is up to the fi rmware to scan the matrix sequentially to determine the status of the buttons. when the buttons are organized in matrix mode any button push must wake the chip up from a shutdown mode. since the buttons are not connecting gpio to grou nd, but connecting an input gpio to some output gpio, the output gpio must be connected to ground du ring the chip shutdown. that is achieved by setting the matrix option control bi t in the gpio latch. when that bit is se t then the gpio[3:1] are actively pulled to ground when the chip is in the shutdown mode and digital logic has no power internally. note that to use the matrix mode the roff option must not be used. in other words, all the pullup resistors must stay in place for all the gpio. there should be values port_matrix=1 and port_roff=0 latched into gpio options control latch. when the matrix mode is latched into the gp io control latch the pullup resi stors of the gpio[3:1] are dis- connected and the pull down transistor on those gpios is activated. important: before invoking a matrix mode the user is responsible for programming all gpio[3:1] as inputs. this is achieved by writing 1 to p0[3:1] and writing 0 to p0con[3:1]. only after that the matrix option can be invoked. if the chip went to shutdown with matrix option set, then it w ill be woken up by any bu tton press of the but- ton matrix. it is a responsibilit y of the user a pplication which must turn the matrix mode off before the soft- ware can scan the button matrix for current button st atus. the button scanning is usually done scanning the matrix driver pins gpio[3:1] with one-cold pattern, applying sequential binary patterns gpio[3:1]=110, 101, 011, and 111 using open drain configuration of the gpio[3:1]. by collecting corresponding responses on the gpio[4,0] or gpio [4,0,9:6], input gpios to the driving one-cold patterns firmware can determine what buttons are currently pushed.
rev. 1.0 113 SI4010-C2 figure 30.4. push button organization in matrix mode pushbuttons connecting the crossing wires: gpio[4] gpio[1] gpio[2] gpio[3] e port_strobe wr: port_matrix gpio[0] = gpio[6] gpio[7] gpio[8] gpio[9] 14 pin package only
SI4010-C2 114 rev. 1.0 30.4. pullup roff and matr ix mode option control both roff and matrix mode options are controlled by the gpio pad itself. the control is implemented as 2 bit latch inside of the gpio pads. both options stay in their used defined states during chip shutdown. in other words, if the chip is in shutdown mode, the digital logic does not have power, but the two gpio latches keep the user set values of those options. the options are controlled by the port_ctrl sfr regist er. the user has to strobe the desired values to the gpio latches by software sequence. the latc h enable is a port_strobe bit in the port_ctrl register. for example, to disable the both matrix and roff options at the beginning of use application, the user code should look like this in assembly: anl port_ctrl, #10011111b ; clear port_matrix and port_roff orl port_ctrl, #10000000b ; set port_strobe=1 anl port_ctrl, #01111111b ; clear port_strobe=0 using silicon labs provid ed masks in the header: anl port_ctrl, #not(m_port_matrix or m_port_roff) orl port_ctrl, #m_port_strobe anl port_ctrl, #not(m_port_strobe) the toggle of the port_strobe from 0 to 1 back to 0 latches the current register values of port_matrix and port_roff. to summarize: to change the values of the matrix an roff options, the following software sequence is required: 1. set the desired values of port_matrix and port_roff bits in th e port_ctrl register. 2. toggle the port_strobe bit in the port_ctrl regi ster from 0 to 1 back to 0 while not changing any other bit in the port_ctrl register. the new matrix and roff control values are latched into the gpio. 3. note that while reading the port_ctrl the current value of the matrix and roff options is read from the gpio, not the value of the write register for the new matrix and roff setting. invoking a matrix mode requires the following sequence: 1. set the gpio[3:1] as inputs, which means writing 1 to the port value and making the driver open drain. 2. latch port_matrix=1 and prot_roff=0 val ues to the gpio option control latch.
rev. 1.0 115 SI4010-C2 in assembly: orl p0, #00001110b ; turn gpio[3:1] as inputs anl p0con, #not 00001110b anl port_ctrl, #not(m_port_matrix or m_port_roff) orl port_ctrl, #m_port_matrix ; set matrix mode and keep resistors orl port_ctrl, #m_port_strobe ; strobe new matrix/roff modes to gpio anl port_ctrl, #not(m_port_strobe) 30.5. special gpio modes control some of the gpio serves multiple purposes. spec ial configuration registers port_ctrl and port_set are used to configure gpio for other purpose then regular gpio. some gpio can server multiple special purposes. table 30.4 shows all the functionality the gpio can as sume along with control signals and priority of the functionality. the lower the priority number, the higher the functional priority. for example, if the functional- ity with priority 1 is programmed, then controls selectin g functionality of priority 2 and above will be ignored no matter what the control settings are.
SI4010-C2 116 rev. 1.0 table 30.4. gpio special roles control and order gpio roles order control comment 0 vpp 1 nvm programming voltage vpp = 6.5 v xo 2 xo_ctrl .xo_ena gpio 3 p0 .0 fixed as input only 1gpio1 p0 .1 p0con .1 matrix, roff ind* port_ctrl 2gpio1 p0 .2 p0con .2 matrix, roff ind* port_ctrl 3 reference clk_ref 1 port_set .port_refen reference interv al clock for frequency counter gpio 2 p0 .3 p0con .3 matrix ind* port_ctrl 4 c2dat 1 automatically ?sto len? from application during c2 transaction. output clk_out 2 port_set .port_clken port_set .port_clkout[0] cannot be used in the development system, since c2 transaction disrupts the output. gpio 3 p0 .4 p0con .4 5 c2clk 1 acts as if a c2 debug clock input of the led driver is not turned on. led driver 2 p0 .5 port_ctrl .port_led[1:0] port forced as output. to read the actual led driver status (on/off) the user should read rbit_data .gpio_led_drive 6 output clk_out 1 port_set .port_clken port_set .port_clkout[1] 14 pin only gpio 2 p0 .6 p0con .6 7gpio1 p0 .7 p0con .7 14 pin only 8gpio1 p1 .0 p1con .0 14 pin only 9gpio1 p1 .1 p1con .1 14 pin only *note: ind stands for ?independent? setting. the matrix and roff modes are controlled in analog pad circuitry.
rev. 1.0 117 SI4010-C2 30.6. led driver on gpio[5] for application mode the gpio[5] is shared with led cu rrent driver. the led current driver provides three levels of led current, 1ma maximum. the current le vels are described in sfr definition 30.6. user can set the current intensity and then control the led on and off by p0.5, port p0 bit 5, as a regular output. there is no need to modify the p0con. 5 bit, since the gpio[5] output driv er is set to be open drain. when the led driver is on by setting the p0.5=1 then the pu lldown output transistor is disabled. the gpio[5] is used as a regular open drain output during the c2 debugging sessions only. during the c2 debug sessions the ide will forcibly dis able the led driver so the led drive will not interfere with the debugging session. th ere will be an option on ide to disable the ?led disable?, but it will have to be used with caution. when the user hits disconnect button on the ide then the ide clears all breakpoint, removes the led dis- able, and runs the application from th e point where it was halted. then the application will control the led. the user then can hit the connect button on the ide to connect to the chip again. for the ide to be able to connect to the chip the led must not be driven (not lit). figure 30.5. gpio[5] led driver block diagram vdd 50k gpio[5]/led 2 debug led disable port_ctrl port_strobe port_roff port_led[1:0] port_5_midrange port_midrange port_matrix port_drv2x p0 p0.7 p0.6 p0.3 p0.2 p0.5 p0.4 p0.1 p0.0 vdd
SI4010-C2 118 rev. 1.0 sfr address = 0x80 sfr definition 30.1. p0 bit76543210 name p0[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 11011111 bit name function 7:0 p0[7:0] port 0 register, gpio[7:0], bit addressable. write appears at the gpio[7:0] outputs, re ad reads directly the gpio input values. write: 0 .. output low value 1 .. output open-drain or high drive value in push-pull mode read: 0 .. gpio pin is at logic low value 1 .. gpio pin is at logic high value special pins: the gpio[0] is input only. write to gpio[0] has no effect. the gpio[5] is output led driver only and requires setting of the proper led drive current. then gpio[5] just turns the led current on (1) or off (0). reading from gpio[5] returns the user intended driver of led (1 .. dr iving, 0 .. off). th e read value will be read as 0 if, for example, the user writes gpio[5] as 1, but the led current value port_ctrl.port_led will be 0. the read gpio[5] value does not represent the actual driving status of the led drive, since the debug logic and c2 can disable t he led. the actual led driving status can be read as rbit_data.gpio_led_drive bit.
rev. 1.0 119 SI4010-C2 sfr address = 0xa4 sfr address = 0x90 sfr definition 30.2. p0con bit76543210 name p0con[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 p0con[7:0] port 0 configuration register, for gpio[7:0]. this bit controls confi guration of each corresponding output bit in p0. 0 .. open-drain 1 .. push-pull if the pin to be input, it must be configured as open-drain and 1 has to be written as output value to it. sfr definition 30.3. p1 bit76543210 name p1[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000011 bit name function 7:0 p1[7:0] port 1 register gpio[15:8], bit addressable. write appears at the gpio[15:8] outputs, read reads directly the gpio input values. same as for p0. only gpio[9:8] are used, wr ite to the rest of the register has no effect, read returns 0 at those bits.
SI4010-C2 120 rev. 1.0 sfr address = 0xa5 sfr address = 0xa0 sfr definition 30.4. p1con bit76543210 name p1con[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 p1con[7:0] port 1 register gpio[15:8], bit addressable. this bit controls confi guration of each corresponding output bit in p1. 0 .. open-drain, pull up resistor connected (see port_roff) 1 .. push-pull, pull up resistor disabled if the pin to be input, it must be configured as open-drain and 1 has to be written as output value to it. only bits [1:0] corresponding to gpio[9:8] are used, write to the rest of the register has no effect , read returns 0 for those bits. sfr definition 30.5. p2 bit76543210 name p2[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 p2[7:0] port 2 register, bit addressable. it is not a port, but a regular register. this register is used as a page msb address byte for xdata addressing in mode, using the pdata memory accesses. the sole purpose for it is to support the pdata model.
rev. 1.0 121 SI4010-C2 sfr address = 0xb5 sfr definition 30.6. port_ctrl bit76543210 name port_ strobe port_ roff port_ matrix port_ drv2x port_5_ mid- range port_ mid- range port_led[1:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 0??01100 bit name function 7 port_ strobe port strobe. strobe the port_matrix and port_roff bits valu es from this register to the gpio pads. the operation requires additional 2 cpu clock to finish after writing 0->1->0 to this bit. when 1 is written to this bit the gpio la tches open and the values of port_matrix and port_off are propagated to gpio pads. soft ware must clear this bit to capture those two bits in the gpio pads internal hv permanent latches. 6 port_ roff port roff mode. roff mode, read from this bit returns the actual roff mode value as reported from gpio pad. when a 1 is latched into the gp io pad internal roff mode hv latch then the gpio roff mode gets invoked. the gp io[1:2] will have thei r pull-up resistors turned off. 5 port_ matrix port matrix mode. matrix mode, read from this bit returns the actual value matrix mode value as reported from gpio pad. when a 1 is latch ed into the gpio pad internal matrix mode hv latch then the gpio matrix mode gets invoked. the gpio[1:3] are driven low with resistor pull-ups disabled. this is intended for matrix button mode to wake up from sleep mode. 4 port_ drv2x increase drive strength by 2x on all outputs. 3 port_5_ midrange input gpio[5] pin trip point set to 45% vdd. 2 port_ midrange input gpio pin trip point set to 45% vdd (except gpio[5]) 1:0 port_led [1:0] led current drive strength. it must be set to non-zero value for led to have any current. this is just a current source setting. the actual turning of the led on and off is controlled by the gpio[5] output bit in p0. 00: led off 01: led current = 0.62*600ua 10: led current = 1.00*600ua 11: led current = 1.62*600ua
SI4010-C2 122 rev. 1.0 sfr address = 0xb6 sfr definition 30.7. port_set bit76543210 name edge_ int1 edge_ int0 port_clkout[1:0] port_ clken port_ refen reserved reserved type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 edge_ int1 edge control for int1. this bit controls whether single edge or both edges invoke the interrupt. 0: single edge, polarity specifie d by neg_int1 in port_intcfg. 1: both edges, which means any edge, invoke int1 interrupt. 6 edge_ int0 edge control for int0. this bit controls whether single edge or both edges invoke the interrupt. 0: single edge, polarity specifie d by neg_int0 in port_intcfg. 1: both edges, which means any edge, invoke int0 interrupt. 5:4 port_ clkout [1:0] select which gpio pin is used as clock output pin. port_clkout[0]: 1 .. clk output at gpio[4], 0 .. normal/other gpio[4] operation port_clkout[1]: 1 .. clk output at gpio[6], 0 .. normal/other gpio[6] operation both outputs can be used simultaneously. the actual clock waveform can be enabled/disabled by port_clken bit, but the gpio configurat ion is purely controlled by port_clkout. 3 port_ clken enable output clock, which is possibly coming out on gpio[4] and/or gpio[6]. this bit is just a clock enab le/disable, it does not configure the gpio for clock out- puts. the port configuration must be done by port_clkout below. the generated clock division is controlled by clkout_set register. if the clock is disabled by port_clken=0 the current period in prog ress will be finished and the output clock will stop as logic 0. 2 port_ refen enable clk_ref reference cl ock to come from gpio[3]. the gpio[3] pad is forced to be an input. there is not need to change p0 or p0con register values, since port_refen has higher priority. 1:0 reserved these bits must be left at 0.
rev. 1.0 123 SI4010-C2 31. clock output generation the device includes an option to be used as a clock generator for other chips connected to the device. the generated clock frequency, clk_out , is derived from the in ternal 24mhz oscillator. system clock division set in sysgen register has no effect on the clk_out frequency. the clk_out is an output of a divider with programmable division from 1 to 31 in an increment of 1. there- fore, the output frequency of the output clock can range from 24mhz to 24mhz/31 = 774khz. the divider has an option to keep the clk_out duty cycle to 1:1 even for odd division ratios. there is an option of at which logic level the clk_out stops when the clock generator is disabled. the clock divider/generator always fi nishes the period it started before it accepts a new division factor clkout_div. it is recommended to fix all the sett ings before enabling the output clock generator. the master enable is port_clken bit in the port_set register. figure 31.1. output clock generator block diagram 24mhz divide by clkout_div[4:0] clkout_set clkout_clr clkout_inv clkout_sym clkout_div clear symmetry 1:1 duty cycle port_set edge_int1 edge_int0 port_clkout port_clken port_refen enable gpio[6] gpio[4]
SI4010-C2 124 rev. 1.0 31.1. register description sfr address = 0x8f sfr definition 31.1. clkout_set bit76543210 name clkout_ clr clkout_ inv clkout_ sym clkout_div[4:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 clkout_ clr clkout clear. write 1 to this bit clears the generated cl ock divider. the generated clock output is forced to 0. reading this bit has clkout_i dle meaning. if read as 1 then it indicates that the clock divider generator is idle. it can be used to wait for the clock to get idle after the user clock output was disabled by port_set.port_clken=0. if this bit is read as 0 the clock division generator by factor 2 and above is running and the current user clock period is still in progress. the user could use this bit to synchronously switch the clkout_div division factor, but it is not necessary. the synchronous clock period switching is built in the hard- ware. see the clkout_div field description of this register. to switch the clocks immediately without waiting for the current pe riod to end, write 1 to this bit. the write 1 to this bit can be combined with setting the new clkout_div value in this register at the same time. 6 clkout_ inv clkout inversion. invert the generated clock. th e inverter is at the very end of the clock generation chain. normally, if this bit is 0, if the gen erated clock is disabled the output is at 0. with this bit set to 1 the output is inverted, therefore the generated clock stops at 1. this bit must be set before customer clock is enabled to the port output by setting port_set.port_clken=1. if ch anged later the clock inversion takes effect imme- diately with possibility of short clock pu lse being generated at the clock output.
rev. 1.0 125 SI4010-C2 5 clkout_ sym clkout symmetry. if this bit set to 1 then the output clock duty cycle is very close to 1:1 irrespective of the division factor. however, the generated clock waveform is a combination of outputs of two flops and therefore might jitter more. if this bit is 0 then for odd division factor there is a single 24 mhz period differ ence in between halves of the generation output clock. this bit must be set before customer clock is enabled to the port output by setting port_set.port_clken=1. 4:0 clkout_ div[4:0] clkout divisi on factor. division factor of the 24 mhz oscillator cl ock for generation of the output customer clock. the enable of the clock is controlled by the port_clken and port_clkout bits in port_set register. the division factors 0 and 1 pass the 24 mhz internal cheap oscillato r output as output clocks. value bigger than 1 is the actual division factor of the 24 mhz. if clkout_sym=0 (recommended), the generat ed clock is an output of a flop. for odd division ratios the first part of the pe riod in logic 0 is one 24 mhz clock cycle shorter than the second high half part of the period of generated clock, assuming clkout_inv=0. if the clock is disabled by port_clken =0 the current perio d in progress will be ? finished. to monitor when th e output gets idle monitor the clkout_clr bit of this register. the clkout_div bit can be changed any time . the new setting will take effect only after the current period finishes. for the new setting to take effect immediately see clkout_clr. bit name function
SI4010-C2 126 rev. 1.0 32. control and system setting registers the following are general system setting control regi sters as well as general purpose scratch pad regis- ters. gpr_ctrl and gpr_data can be used as a general purpose 2 byte sfr register. they do not con- trol any hardware on the device. sfr address = 0xb1 sfr address = 0xb2 sfr definition 32.1. gpr_ctrl bit76543210 name gpr_ctrl[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 gpr_ctrl[7:0] general purpose register. sfr definition 32.2. gpr_data bit76543210 name gpr_data[7:0] type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7:0 gpr_data[7:0] general purpose register.
rev. 1.0 127 SI4010-C2 sfr address = 0x99 sfr definition 32.3. rbit_data bit 7 6 5 4 3 2 1 0 name reserved reserved gpio_ led_ drive xo_ ckgood ods_ empty ods_nod ata reserved reserved type rrr r r r r r reset 000 0 1 1 bit name function 7:6 reserved read as 0x0. write has no effect. 5 gpio_led_drive gpio led drive. actual status of the led drive. if this bit is at 1, then the led driver is actually on. the led driver is controlled by p0.5 bit and the intensity value in port_ctrl register. if the p0.5 bit is read, then it returns user led drive request, which does not reflect the actual led driver status. 4 xo_ckgood crystal oscillator clock good. crystal oscillator xo output is stable. 3ods_empty ods empty. supplementary flag indicating that the ods tx holding register is empty. it can be used as an indication for software to write a new data byte to ods_data register to transmit. this applies to the tx holding register only. see ods_noda ta for the flag related to the actual tx shift register. 2ods_nodata ods no data. supplementary flag that the output digital serializer (ods) tx shift register ran out of data and there is nothing else to transmit. 1:0 reserved reserved. can read either 0 or 1.
SI4010-C2 128 rev. 1.0 33. real time clock timer the si4010 device contains a real time clock (rtc) ti mer. this dedicated timer provides accurate interrupt request pulses in precise time intervals. the device does not contain any hardware nor any battery backed up real time clock. the purpose of rtc timer is to provide accurate time intervals for user application at run time, not an absolute real calendar time. the rtc timer clock source is the internal calibrate d system clock generator. the rtc constant tick gen- erator runs from the selected divided internal system clock, which is a power of two division of the 24 mhz internal oscillator. the frequency ranges from 24 mhz down to 24 mhz/ 128. the rtc tick generated is a constant frequency of 24 mhz/128 wit h tick period 5.33 s and is indepen dent of the system clock division setting sysgen_div in the sysgen sfr register. the user can select what ex act time intervals the rtc ti mer will set its interrupt fl ag. the time interval is programmable to be one of the following: 100 s, 200 s, 400 s, 800 s, 1 ms, 2 ms, and 5 ms. this time is independent of the sele cted system clock divider in the sysgen sfr register. figure 33.1. rtc timer block diagram osc clkc clk_sys clk_osc rtc tick 24mhz ... 24mhz/128 rtc_tick 5.33us sysgen shutdown power_1st rtc_tickclr port_hold sysgen_div rtc rtc_tick to tmr2 & 3 rtc_ctrl rtc_int rtc_ena rtc_clr rtc_div interrupt 24mhz
rev. 1.0 129 SI4010-C2 33.1. rtc interrupt flag time uniformity since 100 s and 200 s pulse duratio n is not exactly an integer multiple of the 24 mhz/128 frequency, the fractional division was used. the 100 s and 200 s pulse durations are uniform on average , when observed over a sufficiently long timer period. in stantaneous time difference in between subsequent 100 s and 200 s pulses is not 100 s or 200 s, re spectively, but fluctuates around those two values. ? 100 s pulse train .. the 100 s pulse train consists of rtc_tick time duration of 19, 19, 19, 18 ticks. that means that 3 subsequent 100 s pulses has time difference of 19 x rtc_tick periods, which is 19 x 5.33 s = 101.33 s. that is followed by a singe duration or 18 x rtc_tick period duration, which is 18 x 5.33 s = 96 s. on average, the 100 s pulse time period is (3 x 19 + 18)/4 x rtc_tick period, which is 18.75 x 5.33 s = 100 s exactly. ? 200 s pulse train .. for 200 s the pulse train consists of rtc_tick time duration of 38, 37 ticks. that means that the pulse train is an alternation train of 38 x 5.33 s = 202.66 s and 37 x 5.33 s = 197.33 s, when on average the duration is (38 + 37)/2 x 5.33 s = 200 s exactly. the pulse trains for 400 s pulses and long er have a uniform, exact, time periods. 33.2. register description the rtc timer is controlled by the rtc_ctrl sfr regist er. if there is a need for precise beginning of the rtc timer period, the internal tick generator can be clea red by writing a bit rt c_tickclr in the sysgen register. the rtc_tick generator runs freely whenever the rtc timer is enabled by rtc_ena=1. if the user needs to clear the rtc timer to synchronize it with some event, writing 1 to rtc_clr will clear the timer, which keeps running. the rtc rtc_tick generator is not clear ed by that event. therefore, there will be up to 5.33 s time uncertainty in the calculated time period. clearing of the rtc rtc_tick generator is achieved by writing 1 into the rtc_tickclr bit in sysgen register. to achieve exact synchronization it is recommended to write 1 into the rtc_tickclr, then 1 to rtc_clr, followed by another 1 into the rtc_tickcl r. in assembly using the m_ masks 8-bit mask notation from the supplied assembly include file: orl sysgen, #m_rtc_tickclr orl rtc_ctlr, #m_rtc_clr orl sysgen, #m_rtc_tickclr the reason for splitting the clear is that the rt c tick output, rtc_tick can also be selected as a time source for tmr2 and tmr3, so there is a need to have separate control over the rtc_tick generator clearing. to get the rtc tick generator running the rtc_ena=1 mu st be set. therefore, even if the rtc interrupt is not used, the rtc timer must be enabled if the user wants to use the rtc_tick as a clock source for tmr2 or tmr3.
SI4010-C2 130 rev. 1.0 sfr address = 0x9c sfr definition 33.1. rtc_ctrl bit76543210 name rtc_int rtc_ena rtc_clr reserved reserved rtc_div[2:0] type r/w r/w w r r r/w reset 00000000 bit name function 7rtc_int real time clock interrupt flag. set after the time interval set by rtc_div fi eld elapses. software must clear the flag. hardware will not clear the flag 6rtc_ena real time clock enable. if set to 1 then the rtc_tick and bottom part of the pulse generator starts running where it left off. if rtc_div >=3 then top half also starts. 0: rtc disabled 1: rtc enabled. 5 rtc_clr real time clock clear. writing 1 will clear the puls e generator but will leave the rtc_tick generator intact. see the rtc_tickclr in the sysgen regist er for clearing th e rtc_tick counter. 0: normal operation 1: rtc cleared 4:3 reserved read as 0x00. write has no effect. 2:0 rtc_div [2:0] real time clock divider. select the divider of the rtc_tick to de termine the interval for the rtc interrupt generation. 000: no interrupt generation 001: 100 s .. it is a 19/19/19/18 divider 010: 200 s .. it is a 38/37 divider 011: 400 s 100: 800 s 101: 1 ms 110: 2 ms 111: 5 ms
rev. 1.0 131 SI4010-C2 34. timers 2 and 3 the si4010 device includes two identic al timers, timer 2 (tmr2) and timer 3 (tmr3). since the timers are identical, the description will refer to timer 2 (tmr2). the reader can r eplace the tmr2 with tmr3 in the text to get the description of timer 3 (tmr3). the desc ription refers to a ?timer? as an alias for either tmr2 or tmr3. timer 2 is a 16-bit timer formed by two 8-bit sfrs : tmr2l (low byte) and tmr2h (high byte). timer may operate in on of the two width modes: ? wide mode .. timer operates as a single 16 bit wide timer controlled by the control bits related to the low half of the timer, like tmr2l_mode, etc. the ti mer sets the tmr2inth bit as an interrupt flag. ? split mode .. timer operates as two independent 8 bit wide times, with related co ntrol bits related to high (h) and low (l) half of the overall 16 bit timer. in each of the width mode s each timer or each half of the time r can operate in two different functional modes: ? timer mode .. the timer runs as a counter counting up, when it overflows it sets corresponding interrupt flag, reloads initial value, an d keeps going, counting up. ? capture mode .. the timer counter is fr ee running counting up. when it overflows it keeps counting up from 0. when an external capture ev ent happens then the current value of the timer is captured in the capture register, the counter keeps counting and will not stop . the interrupt flag is set by the capture event. each timer or timer half can be independently clocked from one of 4 clock sources. clock source can be independently set for each half of the timer in split mode. the clock sources available for each timer half are: 1. current system clock clk_sys . this is 24mhz, possibly divided by n-th power of 2 with n=0, ..., 7. see sysgen sfr register for s ystem clock setting details. 2. current system clock clk_sys divided by 12 .. clk_sys /12 3. rtc timer tick rtc_tick with 5.33us period (24mhz/128) 4. rtc timer 100us pulse. see the rtc section for an important note related to the uniformity of the 100us pulse train. all clock sources are synchr onous with the system clock. the capture event is int0 for tmr2 and int1 for tmr3. they are edge events coming from external gpio and are the same as for the external interrupt generation, int0 and int1. to use these events as capture events they have to be prog rammed exactly the same way as if they were intended to be used for interrupt generation. they could generate int0 and int1 interrupts at the same time when the are being used as capture events for tmr2 and tmr3, respectively. if the timer operates in split mode both halves are completely independent. therefore, all 4 combinations of functionality in split mode, timer/timer, timer/capture, captur e/timer, and capture/capture are possible. each half has separate cl ock selection. the only common thing is th e capture signal, which is the same for both halves in split mode. the only difference in between of tw o halves in capture/capture mode can be the counter clock, set independently for each half.
SI4010-C2 132 rev. 1.0 34.1. interrupt flag generation timer 2 has a single interrupt signal going to interrupt controller. internally, there are 2 interrupt flags, tmr2inth for high half of the timer and tmr2intl for low half of the timer, which are combined to gener- ate the final interrupt signal. the low half has a local interrupt flag enable tmr2intl_en control bit. figure 34.1. timer interrupt generation setting of the interrupt flags depends on the width and functional modes of each timer or its half. ? wide mode l timer mode tmr2inth set if tmr2h overflows ? tmr2intl set if tmr2l overflows l capture mode ? tmr2inth set if capture event happens and tmr2h, tmr2l 16-bit value gets captured ? tmr2intl set if tmr2h overflows. note: this is an exception when low interrupt flag gets set based on the high half of the timer. this is a supplemental information for the interrupt handler about th e capture, indicating that the 16-bit counter overflew in between captures. ? split mode l timer mode ? tmr2inth set if tmr2h overflows ? tmr2intl set if tmr2l overflows l capture mode ? tmr2inth set by capture event when tmr2h gets captured ? tmr2intl set by capture event when tmr2l gets captured each of the modes is described in a separate section. there is a clock selection r egister tmr_clksel common for both timer 2 and timer 3. tmr2ctrl tmr2inth tmr2intl tmr2intl_en tmr2split tmr2h_cap interrupt tmr2l_cap tmr2h_run tmr2l_run
rev. 1.0 133 SI4010-C2 34.2. 16-bit timer with auto reload (wide mode) when tmr2split=0 and tmr2l_cap=0, the timer op erates as a 16-bit timer with auto reload. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the time reload registers (tmr2rh and tmr2rl) is loaded into the timer register as shown in figure 34.2, and the timer high byte overflow flag tmr2 inth (tmr2ctrl.7) is set. if timer interrupts are enabled (see ie and eie1 registers), an inte rrupt will be generated on each timer overflow. additionally, if timer interrupts are enabled and the tmr2intl_en bit is set (tmr2ctr l.5), an interrupt will be generated eac h time the lower 8 bits (tmr2l) overflow from 0xff to 0x00. figure 34.2. timer 16-bit mode block diagram (wide mode) 34.3. 16-bit capture mode (wide mode) when tmr2split=0 and tmr2l_cap=1, the timer operat es in a 16-bit capture mode. the capture event is int0 for timer 2 and int1 for timer 3. it is the same edge event as programmed to generate external interrupt int0 or int1, respectively. the capture even t can be positive edge, negative edge, or both edges of the gpio associated with the int0 and int1. capture mode can be used for measurement of time inter- vals on external signals. timer counts up and overflows from 0xffff to 0x0000 . each time a capture ev ent is received, the con- tents of the timer registers (tmr2h:tmr2l) are latched into the timer reload registers (tmr2rh:tmr2rl). a timer high half interrupt tmr2inth is generated by capture event. additionally, the low byte interrupt flag tmr2intl is set whenever th e timer overflows from 0xffff to 0x0000. this addi- tional information may be used by and application. note that the capture event can also generate its own ex ternal interrupt on top of the timer interrupt, if enabled by the application. also note that if t he capture timer is stopped (tmr2l_run=0) the capture event still captures the current co unter registers (tmr2h:tmr2l) in to the timer re load registers (tmr2h:tmr2rl) and sets the flag tmr2inth. tmr2ctrl tmr2inth tmr2intl tmr2intl_en tmr2split tmr2h_cap interrupt tmr2l_cap tmr2h_run tmr2l_run tmr_clksel tmr3h_mode tmr3l_mode 0 1 tmr2l_run 2 3 clk_sys/12 rtc_tick (5.33us) rtc_pulse (100us) tmr2h_mode tmr2l_mode 2 tmr2l tmr2h tmr2rl tmr2rh clk_sys tmr2l overflow reload
SI4010-C2 134 rev. 1.0 figure 34.3. capture 16-bit mode block diagram (wide mode) 34.4. 8-bit timer/time r mode (split mode) when tmr2split=1, the timer operates as two independent 8-bit timers. each of the 8-bit timers can independently operate in either 8-bit timer or 8-bit capture modes. the only common signals for both 8-bit timers are capture event input signal and the interrup t output signal. therefore, four possible configura- tions are possible in split mode. all of th em are described in the subsequent sections. if tmr2l_cap=0 and tmr2h_cap=0, both halves oper ate as two independent 8-bit timers with indepen- dently set clocks. as the 8-bit timer register increments and overflows fr om 0xff to 0x00, the 8-bit value in the time reload registers (tmr2rh or tmr2rl) is loaded into the co rresponding timer register (tmr2h or tmr2l), and the corresponding byte overflow flag tmr2inth or tmr2intl are set, res pectively. if timer interrupts are enabled (see ie and eie1 registers), an inte rrupt will be generated on each timer overflow. tmr2ctrl tmr2inth tmr2intl tmr2intl_en tmr2split tmr2h_cap interrupt tmr2l_cap tmr2h_run tmr2l_run tmr3h_mode tmr3l_mode 0 1 tmr2l_run 2 3 clk_sys/12 rtc_tick (5.33us) rtc_pulse (100us) tmr2h_mode tmr2l_mode 2 tmr2l tmr2h tmr2rl tmr2rh clk_sys capture int0 tmr_clksel int1 for tmr3
rev. 1.0 135 SI4010-C2 figure 34.4. two 8-bit timers in timer/timer configuration (split mode) 34.5. 8-bit capture/capt ure mode (split mode) when tmr2split=1, tmr2l_cap=1 and tmr2h_cap=1, both halves operate independently in 8-bit capture modes. however, the captur e event is the same for both time rs. the clock sources for each timer are selected independently, so one timer can capture short pulses while the other one long pulses, for example. each 8-bit timer is free running, counts up and overfl ows from 0xff to 0x00. each time a capture event is received, the contents of the timer registers (tmr2h and tmr2l) are latched into the corresponding timer reload registers (tmr2rh and tmr2rl). common capture event int0 (int1 for timer 3) sets both high and low half interrupt flags tmr2inth and tmr2intl at the same time. the capture event can also generate its own external in terrupt on top of the timer interrupt, if enabled by the application. if the capture time r is stopped (tmr2l_run=0), the ca pture event still captures the cur- rent counter register tmr2l into the reload register tmr2rl and sets the flag trm2intl. same indepen- dently applies to the upper half tmr2h with its respective registers and flags. tmr3h_mode tmr3l_mode 0 1 tmr2h_run 2 3 clk_sys/12 rtc_tick (5.33us) rtc_pulse (100us) tmr2h_mode tmr2l_mode 2 clk_sys tmr_clksel 0 1 tmr2l_run 2 3 2 tmr2l tmr2rl reload tmr2h tmr2rh reload tmr2ctrl tmr2inth tmr2intl tmr2intl_en tmr2split tmr2h_cap interrupt tmr2l_cap tmr2h_run tmr2l_run
SI4010-C2 136 rev. 1.0 figure 34.5. two 8-bit timers in capture/capture configuration (split mode) 34.6. 8-bit timer/capt ure mode (split mode) when tmr2split=1, tmr2l_cap=1 and tmr2h_cap=0, the split timers operate one in 8-bit timer mode and the other in 8-bit capture mode. sa me situation happens when tmr2l_cap=0 and tmr2h_cap=1, only the roles of the timer 8-bit halves are reversed. the only difference in between these two scenarios are the interrupt flags settings, sinc e tmr2inth and tmr2intl are not symmetrical. the tmr2intl has a local enable tmr2intl_en. the functi onality of the 8-bit timer and 8-bit capture modes for the respective halves is the same as described above when both halves operate in the same mode. tmr3h_mode tmr3l_mode 0 1 tmr2h_run 2 3 clk_sys/12 rtc_tick (5.33us) rtc_pulse (100us) tmr2h_mode tmr2l_mode 2 clk_sys tmr_clksel 0 1 tmr2l_run 2 3 2 tmr2l tmr2rl tmr2h tmr2rh tmr2ctrl tmr2inth tmr2intl tmr2intl_en tmr2split tmr2h_cap interrupt tmr2l_cap tmr2h_run tmr2l_run capture int0 capture int1 for tmr3
rev. 1.0 137 SI4010-C2 figure 34.6. two 8-bit timers in timer/capture configuration (split mode) tmr3h_mode tmr3l_mode 0 1 tmr2h_run 2 3 clk_sys/12 rtc_tick (5.33us) rtc_pulse (100us) tmr2h_mode tmr2l_mode 2 clk_sys tmr_clksel 0 1 tmr2l_run 2 3 2 tmr2l tmr2rl tmr2h tmr2rh tmr2ctrl tmr2inth tmr2intl tmr2intl_en tmr2split tmr2h_cap interrupt tmr2l_cap tmr2h_run tmr2l_run capture int0 int1 for tmr3 reload
SI4010-C2 138 rev. 1.0 figure 34.7. two 8-bit timers in capture/timer configuration (split mode) tmr3h_mode tmr3l_mode 0 1 tmr2h_run 2 3 clk_sys/12 rtc_tick (5.33us) rtc_pulse (100us) tmr2h_mode tmr2l_mode 2 clk_sys tmr_clksel 0 1 tmr2l_run 2 3 2 tmr2l tmr2h tmr2ctrl tmr2inth tmr2intl tmr2intl_en tmr2split tmr2h_cap interrupt tmr2l_cap tmr2h_run tmr2l_run int0 int1 for tmr3 tmr2rh capture tmr2rl reload
rev. 1.0 139 SI4010-C2 sfr address = 0xc9 sfr definition 34.1. tmr_clksel bit76543210 name tmr3h_mode tmr3l_mode tmr2h_mode tmr2l_mode type r/w r/w r/w r/w reset 00000000 bit name function 7:6 tmr3h_ mode timer 3 high byte mode select. timer 3 high half in split mode. ig nored if timer 3 is in wide mode. 00: clk_sys 01: clk_sys/12 10: rtc_tick = 5.33 s 11: rtc_pulse = 100 s 5:4 tmr3l_ mode timer 3 low byte mode select. timer 3 low half in split mode or fu ll timer in wide mode clock selection. 00: clk_sys 01: clk_sys/12 10: rtc_tick = 5.33 s 11: rtc_pulse = 100 s 3:2 tmr2h_ mode timer 2 high byte mode select. timer 2 high half in split mode. ig nored if timer 2 is in wide mode. 00: clk_sys 01: clk_sys/12 10: rtc_tick = 5.33 s 11: rtc_pulse = 100 s 1:0 tmr2l_ mode timer 2 low byte mode select. timer 2 low half in split mode or fu ll timer in wide mode clock selection. 00: clk_sys 01: clk_sys/12 10: rtc_tick = 5.33 s 11: rtc_pulse = 100 s
SI4010-C2 140 rev. 1.0 sfr address = 0xc8; bit-addressable sfr definition 34.2. tmr2ctrl bit76543210 name tmr2 inth tmr2 intl tmr2 intl_en tmr2 split tmr2h_ cap tmr2l_ cap tmr2h_ run tmr2l_ run type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 tmr2 inth timer 2 high byte interrupt flag. interrupt flag for timer high half in split configuration or overall 16 bit timer in wide configuration. it gets set when the high half of the timer overflows or there is a cap- ture event for the high half. this bit is not automatically cleared by hardware. 6 tmr2 intl timer 2 low byte overflow flag. interrupt flag for the timer lo w half. it gets set when the low half overflows in timer mode or by capture event of the low half in capture mode. software must clear this bit, hardware will not clear it. this bit is set when the low half of the timer overflows even if we operate in wide con- figuration. when in wide configuration and in capture mode this bit is set when the high half of the timer overflows. since in that case the capture event is the same for both halves, the capture event sets the tmr2inth inte rrupt flag. then this tmr2intl can be used as a flag that the timer overflew, serving as an additional 17th timer bit in cap- ture mode in wide configuration. 5 tmr2 intl_en timer 2 low byte interrupt enable. when set to 1, this bit enables timer 2 lo w byte interrupts. the overall timer inter- rupt request signal is : tmr2 interrupt request = tmr2inth | (tmr2intl & tmr2intl_en) 4 tmr2 split timer 2 split mode enable. 0: timer operates in wide configuration as 16 bit timer. the low half controls the whole timer. 1: timer operates in split configuration. both halves are controlled independently. 3 tmr2h_ cap timer 2 high byte capture mode enable. if set then tmr2h high half operates in capt ure mode if the timer is in split configura- tion mode. ignored if the timer operates in wide configuration mode. 2 tmr2l_ cap timer 2 low byte capture mode enable. if set then tmr2l low half opera tes in capture mode if the timer is in split configura- tion, or the whole timer operates in capture mode if in wide configuration mode.
rev. 1.0 141 SI4010-C2 1 tmr2h_ run timer 2 high byte run model. tmr2h high byte enable in split configuratio n. ignored if timer operates in wide con- figuration. 0 tmr2l_ run timer 2 low byte run model. tmr2l low byte enable in sp lit configuration, whole time r enable in wide configura- tion. bit name function
SI4010-C2 142 rev. 1.0 sfr address = 0xca sfr address = 0xcb sfr definition 34.3. tmr2rl bit76543210 name tmr2rl[7:0] type r/w reset 00000000 bit name function 7:0 tmr2rl[7:0] timer 2 capture/reload register low byte. tmr2rl holds the low byte of the capture/reload value for timer 2. lsb byte. two halves are not double buffered. write to each of the halves takes effect immedi- ately. if the timer or respecti ve half operates in capture mode this register holds the capture value. if the timer or respective ha lf operates in timer mode this register holds the reload value. sfr definition 34.4. tmr2rh bit76543210 name tmr2rh[7:0] type r/w reset 00000000 bit name function 7:0 tmr2rh[7:0] timer 2 capture/reload register high byte. tmr2rh holds the high byte of the reload value for timer 2.
rev. 1.0 143 SI4010-C2 sfr address = 0xcc sfr address = 0xcd sfr definition 34.5. tmr2l bit76543210 name tmr2l[7:0] type r/w reset 00000000 bit name function 7:0 tmr2l[7:0] timer 2 low byte actual timer value. in 16-bit mode, the tmr2l register contains the low byte of the 16-bit timer 2. in 8- bit mode, tmr2l contains the 8-bit low byte timer value. sfr definition 34.6. tmr2h bit76543210 name tmr2h[7:0] type r/w reset 00000000 bit name function 7:0 tmr2h[7:0] timer 2 high byte actual timer value. in 16-bit mode, the tmr2h register contains the high byte of the 16-bit timer 2. in 8- bit mode, tmr2h contains the 8-bit high byte timer value.
SI4010-C2 144 rev. 1.0 sfr address = 0xb9 ; sfr definition 34.7. tmr3ctrl bit76543210 name tmr3 inth tmr3 intl tmr3 intl_en tmr3 split tmr3h_ cap tmr3l_ cap tmr3h_ run tmr3l_ run type r/w r/w r/w r/w r/w r/w r/w r/w reset 00000000 bit name function 7 tmr3 inth timer 3 high byte interrupt flag. interrupt flag for timer high half in split configuration or overall 16 bit timer in wide configuration. it gets set when the high half of the timer overflows or there is a cap- ture event for the high half. this bit is not automatically cleared by hardware. 6 tmr3 intl timer 3 low byte overflow flag. interrupt flag for the timer lo w half. it gets set when the low half overflows in timer mode or by capture event of the low half in capture mode. software must clear this bit, hardware will not clear it. this bit is set when the low half of the timer overflows even if we operate in wide con- figuration. when in wide configuration and in capture mode this bit is set when the high half of the timer overflows. since in that case the capture event is the same for both halves, the capture event sets the tmr3inth inte rrupt flag. then this tmr3intl can be used as a flag that the timer overflew, serving as an additional 17th timer bit in cap- ture mode in wide configuration. 5 tmr3 intl_en timer 3 low byte interrupt enable. when set to 1, this bit enables timer 3 lo w byte interrupts. the overall timer inter- rupt request signal is : tmr3 interrupt request = tmr3inth | (tmr3intl & tmr3intl_en) 4 tmr3 split timer 3 split mode enable. 0: timer operates in wide configuration as 16 bit timer. the low half controls the whole timer. 1: timer operates in split configuration. both halves are controlled independently. 3 tmr3h_ cap timer 3 high byte capture mode enable. if set then tmr3h high half operates in capt ure mode if the timer is in split configura- tion mode. ignored if the timer operates in wide configuration mode. 2 tmr3l_ cap timer 3 low byte capture mode enable. if set then tmr3l low half opera tes in capture mode if the timer is in split configura- tion, or the whole timer operates in capture mode if in wide configuration mode.
rev. 1.0 145 SI4010-C2 1 tmr3h_ run timer 3 high byte run model. tmr3h high byte enable in split configurat ion, whole timer enable in wide configura- tion. 0 tmr3l_ run timer 3 low byte run model. tmr3l low byte enable in sp lit configuration, whole time r enable in wide configura- tion. bit name function
SI4010-C2 146 rev. 1.0 sfr address = 0xba sfr address = 0xbb sfr definition 34.8. tmr3rl bit76543210 name tmr3rl[7:0] type r/w reset 00000000 bit name function 7:0 tmr3rl[7:0] timer 3 capture/reload register low byte. tmr3rl holds the low byte of the capture/reload value for timer 3. lsb byte. two halves are not double buffered. write to each of the halves takes effect immedi- ately. if the timer or respecti ve half operates in capture mode this register holds the capture value. if the timer or respective ha lf operates in timer mode this register holds the reload value. sfr definition 34.9. tmr3rh bit76543210 name tmr3rh[7:0] type r/w reset 00000000 bit name function 7:0 tmr3rh[7:0] timer 3 capture/reload register high byte. tmr3rh holds the high byte of the reload value for timer 3.
rev. 1.0 147 SI4010-C2 sfr address = 0xbc sfr address = 0xbd sfr definition 34.10. tmr3l bit76543210 name tmr3l[7:0] type r/w reset 00000000 bit name function 7:0 tmr3l[7:0] timer 3 low byte actual timer value. in 16-bit mode, the tmr3l register contains the low byte of the 16-bit timer 3. in 8- bit mode, tmr3l contains the 8-bit low byte timer value. sfr definition 34.11. tmr3h bit76543210 name tmr3h[7:0] type r/w reset 00000000 bit name function 7:0 tmr3h[7:0] timer 3 high byte actual timer value. in 16-bit mode, the tmr3h register contains the high byte of the 16-bit timer 3. in 8- bit mode, tmr3h contains the 8-bit high byte timer value.
SI4010-C2 148 rev. 1.0 35. c2 interface the devices include an on-chip silic on laboratories 2-wi re (c2) debug interface in-system debugging with the production part installed in the end application. th e c2 interface uses a clock signal (c2clk) and a bi- directional c2 data signal (c2dat) to transfer informa tion between the device and a host system. the c2 interface is intend ed to be used by the silicon labs or third party development tools. it is not intended to be used for any other purpose. it can be completely disabled per user programming for fully programmed chips. 35.1. c2 pin sharing the c2 protocol allows the c2 pins to be shared wit h user functions so that in-system debugging. this is possible because c2 communication is typically perfo rmed when the device is in the halt state, where all on-chip peripherals and user software are stalled. in this halted state, the c2 interface can safely borrow the c2clk (gpio[5]) and c2dat (gpio[4]) pins. in most applications, external resistors are required to isolate c2 interface traffic from the user applicat ion. a typical isolation co nfiguration is shown in figure 35.1 along with the connec tion to the standard silicon labs 10-pin debugging in terface header. figure 35.1. 10-pin c2 usb debugging adapter connection to device gpio5 c2dat c2clk vdd gpio4 vdd device 12 34 5 7 9 6 8 10 1k 1k vdd vdd 1k vbus (~ +4.6v) can be used to generate local vdd 50k 50k gpio[4] for application bidirectional use, isolated from the c2 r1 r2 r4 usb debug adapter 10 pin header connector 470 led 1ma max tms c2clk 1k5 sw_gpio4 r6 r5 if pushbutton on keyfob development board, then it has to be isolated by r5 for debugging chain to work, led must be isolated by r6
rev. 1.0 149 SI4010-C2 on this device the gpio[5] is shared with the led curr ent driver, which can drive up to 1ma of current to the ground. normally the led will be co nnected in between the gpio[5] an d vdd. for c2 to work the led driver is disabled during debugging sessions, so even if the user code tries to turn the led on, that opera- tion will not interfere with c2 debug transactions and the actual led cu rrent driver will not be turned on. whenever the user disconnects the id e from the device by hitting the disconnect button on the ide, the ide clears all the breakpoints, clears the led driver disable (enables the led), and runs the currently loaded user application residing in the code/xdata ram from the current position where the code was halted. if ide is disconnected from the device the user application behaves ex actly as programmed, with the led driver driving the led per user application. the user then can connect to the device through ide by hitting the connect button. the connection is only possible when the led driver is not active. upon connection the ide will disable the led driver for the duration of the debug se ssion (until the device is disconnect -ed). the gpio[4] can be used as a bidirectional input/output by a user application, but a resistive network has to be used to isolate the gpio[4] from the c2 transactions, as shown in figure 35.1. instead of the usb debug ad apter the user can also use silicon labs toolstick devel opment tool. the toolstick has a pcb edge 14 pin connector. connection in between the device and the toolstick for soft- ware development and debugging is in figure 35.2.
SI4010-C2 150 rev. 1.0 figure 35.2. 14-pin c2 toolstick connection to device gpio5 c2dat c2clk vdd gpio4 vdd device vdd vdd 50k 50k 470 led 1ma max 1k5 sw_gpio4 r6 r5 if pushbutton on keyfob development board, then it has to be isolated by r5 for debugging chain to work, led must be isolated by r6 1k vbus (+5v) can be used to generate local vdd gpio[4] bidirectional for application use, isolated from the c2 r2 toolstick pcb edge connector 12 34 9 11 10 14 78 56 12 13 1k vdd vdo (+3.3v/200ma) can be used directly as local vdd r4 1k r1
rev. 1.0 151 SI4010-C2 36. ide development enviro nment and debugging chain the development platform will be provided by silicon la bs. the debugging chain co nsists of an evaluation board or an evaluation keyfob, usb debug adapter or a usb based toolstick, and the silicon labs ide development environment. the debugging chain is using the c2 two wire interface to provide an on-chip debugging capability. the environment can load the standard omf-51 object and symbol file only, not any proprietary extensions of that format as used by some tool manufacturers. fo r example, on keil platform it means that the bl51 linker must be used. the ide will not load outputs generat ed by the keil lx51 linker. on raisonance plat- form the output is the omf-51 comp liant and the file extension is aof. the ide debugging environment has means to reset the chip without cycling the power. by pressing the reset inside of the ide the digital part of the device is reset and device startup boot sequence is invoked. all registers are reset to their initial states and all of the factory values are refreshed in ram and regis- ters. if the part is a factory part, the previously loaded code/xdata ram content is not disturbed. if the part is a user part then the user data region is l oaded as well, overwriting t he content of the code/xdata ram. using ide is the only way to reset th e chip without cycling the power to it or shutting it down and waking it up. 36.1. functionality limitations whil e using ide development environment even though using the silicon labs ide development environment preserves almost all of the chip func- tionality, there are some limitations the user should be aware of. given that the code is running from ram and that the c2clk shares the pin with led output curr ent driver (gpio[5]), they are two functionality lim- itations for code deve lopment while using ide: 1. the user cannot put a factory or user chip into the shutdown mode and then wake it up by pressing a button (pulling any of the gpio to ground). when the chip is in shut down mode, the power to all digital is lost and therefore t he ram content with the user code will get erased. 2. the led driver cannot be used when the device is connected to the debug adapters (usb debug adapter or a toolstick). 3. once the part is finalized, programmed as run part, no further debugging is possible.
SI4010-C2 152 rev. 1.0 36.2. chip shutdown limitation while developing firmware on an unprogrammed chip the user cannot call the api function vsys_shutdown () to shutdown the chip without loosing the ram code downloaded by ide. instead, the user should comment out the call to t he shutdown function and replace it with a temporary code, which monitors a button press, actually monitori ng p0 and p1 port inputs based on the user current port settings. if the button is pressed (input port val ue read as 0) then the long jump to address 0x0000 (ljmp 0x0000) should be executed. this would mimic t he functionality of the chip shutdown and push but- ton wakeup. the limitation of this approach is that the digital logi c is not reset and the current values of all the digital registers are preserved, while during the real shutdo wn and wakeup they are asynchronously reset during the process and the whole boot process is invoked. therefore, it is advisable not to re ly on the reset values of any peripheral control registers and during the user application peripheral initialization the initial value should by forced to the registers by using mov instructions rather then using orl and anl instructions to set or clear particular bits while relying on the sfr registers reset values. 36.3. led driver usage whil e using ide debugging chain to maximize utilization of the package pins the led current driver output is shared with the debug chain clock signal c2clk on the gpio[5]. the debugging ch ain internally disables the led driver while the device is connected to the debuggi ng adapter. user can develop the code as if the led were present without interfering wit h the debugging chain. the led driver will not get turn ed on even if the user application code requests the driver to be turned on. to share the led and c2clk functionality on a single pin and be able to use ide for debugging there are some limitations and rules to follow. figure 35.1 an d figure 35.2 show the re commended connection of the debug adapters to the device in the user application. note that the led must be isolated by the 470 resistor for the debugging chain to work. if the debu gging in the user application is not needed then the 470 resistor is not needed either. facts about using the led with ide chain: 1. the ide chain can connect to the device only if th e led current driver is off and the led is not lit. 2. once the ide chain is connected to the device it blocks the device led driver. therefore, the application can be written in a normal fashion us ing led as desired in the final application without worry of being disconnected from the debug chain. t he only limitation is that the led will not be lit from the application during the id e debug session. the user will still observe led activity, but that activity is related to the debug chain communicating with the device, not the user application driving the led. 3. once the ide chain is disconnec ted from the device (by pressing disconnect button in ide, for example), the device is released from halt and at the same time the blocking of the led driver is removed. from that point on the application beha ves and runs as regular application and the led activity reflects what the app lication desires to do with led. 4. if the user wants to reconnect the ide to the devi ce the only requirement is that the led must not be lit by the application at that moment. therefore, if for whatever reason the device user software is stuck in an infinite loop and dr iving the led constantly, the ide ch ain will not be able to connect to the device. in such situations the device power has to be cycled to invoke internal power on reset by unplugging the keyfob from the programming or toolstick boards and replugging again. see item 1. above.
rev. 1.0 153 SI4010-C2 for example, on the keyfob battery backed up develo pment platform the user can disconnect the keyfob from the debugging platform (programming board or directly from the toolstick) and walk around with running application using led as desired by the applic ation. the only thing the user has to do is to disconnect the keyfob from the ide by pressing the disconnect button. the led gets enabled and the application runs from the point where the applicatio n is currently halted. to run the application from the very beginning, the user must press reset on the ide before pressing disconnect .
SI4010-C2 154 rev. 1.0 37. additional reference resources ? an369: antenna interface for the si401x transmitters ? an370: si4010 software programming guide ? an511: si4010 nvm burner user's guide ? an515: si4010 key fob development kit quick-start guide ? an518: si4010 memory overlay technique ? an526: si4010 rom 02.00 api ad ditional library description ? an577: si4010 nvm read reliability analysis
SI4010-C2 rev. 1.0 155 d ocument c hange l ist revision 0.1 to revision 0.2 ? completely revised data sheet revision 0.1 to include mcu operation ? reformatted data sheet to correspond with mcu data sheet format ? removed rke application, focus on general mcu + tx usage ? included 14p soic package and pin information ? updated section ?4. ordering information? on page 15 ? updated section ?10. electrical characteristics? on page 28 revision 0.2 to revision 0.5 ? updated data sh eet for revision b and c silicon ? changed standby supply current to < 10 na ? increase data rate to 100 kbaud for fsk and 50 kbaud for ook ? corrected maximum clock frequency of the lposc to 24 mhz ? updated section 2. ordering information to reflect the revision b and c silicon ? updated table 7.3 dc characteristics to reflect revision b and c silicon ? updated table 7.4 si4010 rf transmitter characteristics to reflec t revision b and c silicon ? fixed block diagram in figure 8.1. test block diagram with 10-pin msop package ? updated section 10. system description text for revision b and c silicon ? updated section 11. power amplifier text for revision b and c silicon ? updated section 23. system boot and nvm programming for revi sion b and c silicon ? updated section 36. additional reference resources to include new application notes revision 0.5 to revision 0.6 ? removed revision b part numbers and replaced with revision c part numbers SI4010-C2-gt and si4010- c2-gs revision 0.6 to revision 1.0 ? updated electrical specific ations to final values.
SI4010-C2 156 rev. 1.0 c ontact i nformation silicon laboratories inc. silicon laboratories inc. ? 400 west cesar chavez ? austin, tx 78701 ? please visit the silicon labs technical support web page: ? https://www.silabs.com/support/pages/contacttechnicalsupport.aspx ? and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademark s or registered trademarks of their respective holders the information in this document is believed to be accurate in al l respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no re sponsibility for errors and omissions, and disclaims responsibi lity for any consequen ces resulting from the use of information included herein. additi onally, silicon laborator ies assumes no responsibility for the fun ction- ing of undescribed features or parameters. silicon laboratories re serves the right to make change s without further notice. sili con laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does silicon laboratories assume any liabi lity arising out of the application or use of any product or circuit, and specifi cally disclaims any and all liability, including without limitation consequential or incident al damages. silicon laboratories product s are not designed, intended, or authorized for use in applications in tended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a si tuation where personal injury or death may occur. should buyer purchase or use silicon laboratories prod ucts for any such unintended or unauthorized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

▲Up To Search▲

Price & Availability of SI4010-C2

	To Download SI4010-C2 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .